- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...refining design and timing constraints for seamless physical design closure. As part of this… more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... * Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience. * Verilog/System Verilog programming experience. * Interactive… more
- Cisco (San Jose, CA)
- …are received. Meet the Team Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for ... leadership in delivering successful products. * Prior experience in managing ASIC design flow (architecture, micro-architecture, RTL, Synthesis, functional… more
- Cisco (San Jose, CA)
- …and implementation of SDC for various timing modes in the chip. * Collaborating with physical and ASIC design teams to resolve timing and routing congestion ... being developed in the industry. Your Impact As an ASIC Engineering Technical Leader, you will be...will act as a bridge between cross-functional teams, including physical design , verification, and software, to ensure… more
- Cisco (San Jose, CA)
- …Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture ... bugs and close code coverage. * Work closely with physical design team to close design...work with SDK and Software teams as part of ASIC development to create a seamless handshake between hardware… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose,...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Broadcom (San Jose, CA)
- …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
- Broadcom (San Jose, CA)
- …route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. Participate in large complex design ... Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC implementation engineer with demonstrated expertise in multiple disciplines including… more
- Cisco (San Jose, CA)
- …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... a relevant position opens. Who You'll Work With The ASIC Group works closely with other development teams within...silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability… more
- Broadcom (San Jose, CA)
- …clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. Chip level expertise in DRC/LVS Calibre tools. ... Sign-In before you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines including… more
- Broadcom (San Jose, CA)
- …the globe connected. Our ASIC products division is looking for senior, physical design engineering veterans to guide teams designing some of the industry's ... Candidate Account, please Sign-In before you apply.** **Job Description:** Technical Lead for Physical Designs Are you...Well verse in EDA tools for physical design verification and sign-off. 6. Knowledge of ASIC… more
- Cisco (San Jose, CA)
- …to physical design signoff activities. What You'll Do You will be part of ASIC physical design Team which is responsible for full Chip physical ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose,...-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to integrating such high power devices into complex scalable enterprise grade hardware. The design / verification / physical design of these ASICs pushes ... particular position requires the individual to be part of ASIC Design effort of the next generation...For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of… more
- Cisco (San Jose, CA)
- …are received. Who We Are Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for ... successful products. * Prior experience in managing both software and ASIC design flow (architecture, micro-architecture, RTL, Synthesis, functional… more
- Cisco (San Jose, CA)
- …as per need for verification robustness. * Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with ... and automate workflows. * Experience working with one or more of the following physical design tools, such as Cadence, Innovus, Synopsys IC Compiler, or Fusion… more
- Broadcom (San Jose, CA)
- …high overall manufacturing yield. The candidate should have a strong understanding of VLSI and ASIC physical design 12+ years of experience w/ a deep ... Candidate Account, please Sign-In before you apply.** **Job Description:** ** Technical Skills/ background:** The Design Architect/ Lead...that will lend itself to seamless closure in the physical design backend flows, help define and… more
- Western Digital (Milpitas, CA)
- …systems architecture + Multi-disciplinary experience, including familiarity with Firmware, HW, and ASIC design PREFERRED: + Knowledge of PCIe Gen5/6 technology ... collaboration with ASIC , HW, Firmware, and Validation teams to navigate technical challenges and identify the most beneficial solutions. You will be tasked to… more
- Broadcom (San Jose, CA)
- …and built-in self-test (BIST). * General knowledge of semiconductor technology and ASIC design flow including Verilog simulation and timing analysis. Verilog ... skill levels. * Ability to multitask and manage multiple technical issues in parallel. * Well organized, methodical, and...ASIC customers on their custom silicon products during design , bring-up, as well as debugging performance or HBM… more
- Broadcom (San Jose, CA)
- … design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing closure, and ... Technical Leadership and Domain Expertise:** + Lead the design and implementation of advanced digital blocks and subsystems....and Timing Closure:** + Perform synthesis and work with physical design teams to achieve timing closure… more
- Qualcomm (Santa Clara, CA)
- … Design (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... professional experience in one or more of the following technical tracks: **_GPU_** + Engineering design and...level simulation, waveform viewers + C, C++, Python **_Digital Design /DV_** + RTL development for modem physical … more