• Hardware Test Engineer

    Palo Alto Networks (Santa Clara, CA)
    …responsible for the manufacturing capabilities to build our next-generation network firewalls. As a Hardware Test Engineer ( DfT ), you will be responsible ... coverage and serviceability with ICT and boundary scan + Drive DfT and test coverage analyses from early Prototype design stages with HW/SW design engineering… more
    Palo Alto Networks (10/30/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    …the implementation and post silicon validation flows. * Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, ... Jose, CA office location Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and ...development of test benches to verify comprehensive Design-for- Test ( DFT ) architecture that supports ATE screening,… more
    Cisco (10/17/24)
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  • CPU DFT Engineer

    Qualcomm (Santa Clara, CA)
    …digital transformation to help create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers, implementation ... engineers and test engineers to verify the DFT and...Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or… more
    Qualcomm (11/01/24)
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  • Hardware Test Engineer

    Teradyne (San Jose, CA)
    …responsive, flexible, and able to succeed within an open collaborative peer environment. As a Hardware Test Engineer you will be responsible for defining and ... implementing manufacturing test strategy for new hardware devices. You...are built free of manufacturing defects. + Understanding of DFT (Design for Test ) and DFM (Design… more
    Teradyne (11/16/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    …to physical design signoff activities. What You'll Do * Responsible for implementing the Hardware Design-for- Test ( DFT ) features that support ATE, in-system ... Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for...logic & IP integration; familiarity with functional verification * DFT CAD development - Test Architecture, Methodology… more
    Cisco (11/01/24)
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  • Hardware Test Engineer INTL…

    Insight Global (San Jose, CA)
    Job Description Insight Global is seeking a experienced Test Engineer to join a large networking company in the Bay Area. You will be joining the Silicon ... Operations team focusing on ATE test bring up in the post silicon lifecycle. You...development and debug to provide insights to production and DFT . Salary expectations for this role range from $36.00-$39.00/hour… more
    Insight Global (11/16/24)
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  • Senior Board Test Engineer

    NVIDIA (Santa Clara, CA)
    We are looking to hire a Senior Board Test Engineer who will work in the Test Solutions Group at NVIDIA developing manufacturing GPU/CPU test solutions ... today! What you will be doing: + Define manufacturing hardware test solutions that translate into methodologies...and validation infrastructure. + Review and provide feedback for DFT in the early design stages. + Debug complex… more
    NVIDIA (11/12/24)
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  • Test Timing Engineer

    Cisco (San Jose, CA)
    …of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of ... Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and...timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
    Cisco (11/08/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    …working out of the Milpitas/San Jose office location. Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's ... Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes,...in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend… more
    Cisco (10/23/24)
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  • Senior Staff Engineer , Electrical Design

    Renesas (San Jose, CA)
    Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... logic equivalent checking + Creating documentation targeting design, verification, and test groups + Assisting with new feature proposal, definition, documentation,… more
    Renesas (11/09/24)
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  • Sr. RF Product Engineer

    Qualcomm (Santa Clara, CA)
    …Qualcomm Atheros, Inc. **Job Area:** Engineering Group, Engineering Group > Hardware Engineering **General Summary:** **Job Overview** The product engineering role ... support tasks. Fulfilling these responsibilities will involve early engagement on DFT and execution strategies, characterization of product performance across bench… more
    Qualcomm (10/30/24)
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  • Senior System Level Product Engineer

    NVIDIA (Santa Clara, CA)
    …a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to making a difference in the world through ... As a member of this team, you are responsible for developing procedures and test specs for manufacturing line with an innate understanding of product quality and… more
    NVIDIA (11/02/24)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    …our architecture and the collaborate with Quality Assurance engineers to deliver great test coverage and improve the Hardware quality. + Coordinate with internal ... Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA...Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most… more
    NVIDIA (10/16/24)
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  • ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We ... craft the networking hardware for Enterprises and Service Providers, the Public Sector,...talent and vast ASIC development expertise in design, DV, DFT , physical design, and post-silicon validation The team comprises… more
    Cisco (10/28/24)
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  • SOC Design Top Level Assembly Methodologies…

    NVIDIA (Santa Clara, CA)
    …our diverse family today! The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design and methodologies. What you'll be ... improve our RTL top-level assembly process and tool set + Top-level assembly: Test new code/features and Address questions and concerns, in addition to developing… more
    NVIDIA (10/15/24)
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