- Cadence Design Systems, Inc. (San Jose, CA)
- …make an impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC ... include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development + Working knowledge of a set of common SerDes standards and… more
- Skyworks (San Jose, CA)
- …Description We, at Skyworks are seeking an experienced, industry professional for the role of Principal Power Amplifier/RF IC Design Engineer at our San Jose ... who together can change the way the world communicates. Job Responsibilities Principal Power Amplifier/RF IC Design Engineer is responsible for design … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …driving customer engagements, you will enhance your in-depth knowledge in nanometer design , unlock unique expertise in digital design implementation, and level ... and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts...and Static Timing Analysis is required Prior experience with IC digital implementation flows and backend EDA tools including… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …drive Pre-sales and Post-sales activities at advanced nodes for Cadence Digital IC products. The qualified candidate will have hands-on experience with Timing, Emir, ... Characterization & Simulation tools, and good circuit design knowledge to help enable Signoff solutions at customer...for myriad circuits including memory designs and mixed signal design + The SE will participate in technical benchmarks,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …in collaboration with R&D to help support advanced verification flows to secure design wins Champion the customer needs and work closely with R&D and marketing ... technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design… more
- Broadcom (San Jose, CA)
- …well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer, the ideal candidate will be responsible for the 3nm high speed ... EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and...12+ years, or ME plus 10+ years, in deep-sub-micron IC physical designs, or equivalent experience Experience with TCL… more
- Western Digital (Milpitas, CA)
- …will work in the Packaging R&D group on the modeling and simulation, design of experiment, and testing across semiconductor packaging, flash memory product and host ... DUTIES AND RESPONSIBILITIES: + Responsible for influencing package and product design by addressing the structural integrity and reliability issues in particular… more
- ManpowerGroup (San Jose, CA)
- …and layout size optimization of CMOS JI and SOI + Collaborate with Analog and Power IC design engineers in Asia and the US + Manage tape-out process, data ... Mobile, Consumer, IoT, and Industrial applications is seeking an experienced Principal Layout Engineer. **RESPONSIBILITIES:** + Layout of Power and Analog integrated… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …in the context of multiple flows including high speed signal and/or power design , signal and power integrity. Design experience and industry knowledge of ... Signal, Power, and Thermal analysis for IC , package, and PCB designs are required. The candidate...Electromagnetics, Thermal, and RF related to Package and PCB Design are required. Candidate should have experience in Cadence… more
- Qualcomm (San Jose, CA)
- …(eg, RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. * Writes and reviews ... for all. As a Qualcomm Digital ASIC Engineer, you will define, model, design , optimize, verify, validate, implement, and document IP (block/SoC) development for a… more
- Qualcomm (Santa Clara, CA)
- …Power Implementation; WiFi or WLAN; Power Optimization; ARM IP/Coresight based debug design ** Principal Duties and Responsibilities:** * Leverages advanced ASIC ... Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC ...and design of multiple complex blocks/SoC or IC Packages. * Writes detailed technical documentation for highly… more
- Qualcomm (Santa Clara, CA)
- …(eg, RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. * Writes and reviews ... **General Summary:** . Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …leadership qualities. Position Requirements: This position requires a solid understanding of IC design process/methodology in analog and mixed-signal design . ... Hands-on knowledge / experience on analog and mixed-signal physical Design / Debug /would be a plus. The role...and hands-on experience of complete analog Back-end flow from design entry, Basic layout editing to advance automation flows… more