- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Cisco (San Jose, CA)
- …noise, while managing ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA ... practices. * Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $100,100 to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to enable new and differentiating technologies.. + In this role, the Solutions Engineer (SE) is expected to work both independently and in collaboration with other ... team members to address customer issues and to identify new opportunities or Risk that are linked to those activities + The SE will interact with Product Engineering/RnD Team as well as Key Technologists at customer site to develop and enable new… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...which is the primary task. + Develop flows/recommendations on STA and PNR in deep submicron physical effects aging,… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...practices. * Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Cisco (San Jose, CA)
- …as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, partitioning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world! We are currently looking for a SRAM Timing Engineer to join our team of dedicated engineers developing custom SRAM circuits that help ... identify improvements and solutions and deploy newer features. + Lead implementation of STA solutions for multiple circuit design and technology teams and 3rd party… more
- Broadcom (San Jose, CA)
- …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... time silicon. Primary expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. Candidate should extremely proficient in… more
- Broadcom (San Jose, CA)
- …timing constraint file + RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA , RTL/gate level simulations & silicon debug + Scripting for various IC ... design tasks such as STA , equivalency checks, test bench, simulations, synthesis, etc. + prepare block level resource requirements & development schedule + generate… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... is a must + Competence in developing design constraints for synthesis, STA and P&R hand-off + Experience with gate-level simulations, causes and implications… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design ... place and route, clock methodology, power planning and analysis, timing closure, STA , signal integrity and physical design checks. + Participate in large complex… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... to verify them at circuit level in both spice and transistor level sta . + Understanding crosstalk, noise, OCV, timing margins. Familiarity with Clocking specs:… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + ... our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! The base… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... how to verify them at circuit level in both spice and transistor level STA . + Understanding crosstalk, noise, OCV, timing margins, Clocking specs (jitter, IR drop,… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + Strong ... world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! #LI-Hybrid… more