- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... partitioning, timing budget generation, power planning, top-level PnR, CTS, block...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... fully verified design by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... checks, etc. + Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to have real ... to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/ timing clean design. + Support post-silicon validation activities. + Work with… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers ... BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD)...+ You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing… more
- Qualcomm (San Jose, CA)
- …to help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design, optimize, verify, validate, implement, ... degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...clock information to GPU, CPU and SOC verification team, timing and DFT teams. You will use Perl to… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing . + Good knowledge of extraction, device physics, STA methodology and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 5+ years experience in ASIC Design and Timing . + Proven understanding of circuit design and spice simulations.… more
- Qualcomm (Santa Clara, CA)
- …such as OFDM and OFDMA modulators and demodulators, transmit beamforming, timing and synchronization, RF impairment correction, adaptive filters . Working with ... to obtain a fixed-point/finite-precision C/C++ model that is realizable in optimized ASIC hardware . Converting the finite-precision models into ASIC hardware… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + ... reviews + Cover digital backend design from synthesis, static timing and logic equivalent checking + Creating documentation targeting...route netlists + Fluent in Verilog RTL coding and ASIC design methodology is a must + Competence in… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Logic Design Engineer ! Asa member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and ... tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for the ... some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market over the last...blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. . Static and… more
- Qualcomm (Santa Clara, CA)
- …degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree ... in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science,… more