- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. NVIDIA's ASIC-PD Methodology organization is driving the next generation of AI-assisted timing ... closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead end-to-end solution development - spanning data generation, model… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... with multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Custom Timing Engineer to join our dynamic and growing Circuit Solutions Group! If you are looking for a ... performance and reliability of Nvidia's next generation products. + Develop timing models and methodology for custom macro design at transistor level along with… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our ... equivalent experience + 6+ years of experience in VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design… more
- NVIDIA (Santa Clara, CA)
- …complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is ... equivalent. + Strong fundamentals in digital design, system and microarchitecture, timing , clocking, power, noise, and control systems; Deep understanding of… more
- NVIDIA (Santa Clara, CA)
- …+ Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Strong understanding of physical design implementation ... eg: physical synthesis, placement, routing, logic restructuring, etc. + Should be a power user of synthesis and/or place and route EDA tools from Synopsys (DC/FC), Cadence (Genus/Innovus) + Good debugging and problem-solving skills + Strong interpersonal… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... from concept to first customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX...Doing: + As a key member of our DFX Methodology Team, you will play a critical role in ... and software teams. + Partner with design, verification, synthesis, timing , and backend teams to ensure cohesive integration. +...is a plus. + Deep expertise in DFT design, methodology , and implementation. + Familiarity with related domains such… more
- NVIDIA (Santa Clara, CA)
- …see how you can make a lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What you'll be doing: + Work ... Work closely with architects, chip leads, and customers on SoC IP design, timing closure, power analysis, methodology alignment, and program execution, ensuring… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Circuit Design Engineer ! NVIDIA stands at the intersection of hardware excellence and AI breakthrough, where every line of code ... layout delivery. + Integrate AI/ML techniques directly into the design process and methodology . + Be a mentor/technical lead for junior team members. What we need… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's ... the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead...fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing Digital design experience The annual salary range for… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, ... and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and...chip and block level. + Experience with CDC, static timing analysis methodologies and relevant tools. + Exposure to… more