- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep ... understanding of timing constraints, such as clock groups, various exceptions, clock... constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding ... Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing ...and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools… more
- Cisco (San Jose, CA)
- …development - Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation ... in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend...What You'll Do * Responsible for implementing the Hardware Design-for- Test (DFT) features that support ATE, in-system test… more
- Qualcomm (Santa Clara, CA)
- …positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools ... responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning,… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... verification reviews + Cover digital backend design from synthesis, static timing and logic equivalent checking + Creating documentation targeting design,… more
- Qualcomm (Santa Clara, CA)
- …. Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and demodulators, transmit ... beamforming, timing and synchronization, RF impairment correction, adaptive filters ....with the verification engineers to develop unit-level and integrated-level test -benches . Debugging the designs in stand-alone and integrated… more
- Arrow Electronics (San Jose, CA)
- … Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/ Test ) handling, block and top level static timing analysis, ECO ... generation at top level, handshaking with blocks for timing /functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to design ... micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and using the latest… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and...define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need… more
- NVIDIA (Santa Clara, CA)
- …a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to making a difference in the world through ... As a member of this team, you are responsible for developing procedures and test specs for manufacturing line with an innate understanding of product quality and… more
- Broadcom (San Jose, CA)
- …before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition including micro-architecture ... crossing issues in the design + Collaborate with verification team on test plan development, debugging, and coverage closure + Collaborate with physical design… more
- Sierra Nevada Corporation (Fremont, CA)
- Firmware design engineer will perform design, development, documentation, integration, test and debug of FPGA and SoC architecture for DoD systems. Firmware ... design, simulation and verification, design documentation generation, firmware integration and test . Skills required include firmware design of FPGAs and SoCs.… more
- Teledyne (Milpitas, CA)
- …closure + Verify proper operation of your circuit via system level test with test hardware + Work with the verification engineer to validate your circuit in ... on a team that wins. **Job Description** Design and test FPGA circuitry for next generation Test and Measurement Tools **Detailed Description:** + Define logic… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture and ... of RTL design to target power, performance, area and timing goals + Write design documents including detailed interface...+ Work with Verification Engineers to develop specifications and test plans. Ensure robust design and complete coverage +… more
- Teradyne (San Jose, CA)
- We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, ... Teradyne's test technology ensures your device works right the first...with our customer base. We are seeking an Electrical Engineer for our Nextest division to develop and maintain… more
- Vector Atomic (Pleasanton, CA)
- …is building quantum devices for applications including GPS-free navigation and timing , geophysical exploration, and telecommunications. We are focused on delivering ... and geophysical exploration. This jack-of-all-trades role requires a skilled and flexible engineer capable of operating in a dynamic R&D environment. The ideal will… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **R&D Staff Engineer ** The ideal candidate will have expertise in integrated-circuit process ... device fabrication and operation, device modeling and circuit design, test development and execution, device-level reliability failure mechanisms and testing,… more
- Broadcom (San Jose, CA)
- …and physical memory models + Document the design specifications, behavioral description, and timing diagrams + Specify silicon test plan and correlate silicon to ... the physical macro + Integrate characterization flow to extract timing and power information + Develop scripts to automate...DFT schemes and chip level integration + Familiar with test setups, silicon testing and debug + Proficient in… more
- Vector Atomic (Pleasanton, CA)
- …is building quantum devices for applications including GPS-free navigation and timing , geophysical exploration, and telecommunications. We are focused on delivering ... for the real world. We are hiring a Navigation Engineer to join our team of scientists and engineers...sensors from top-level navigation system performance requirements. + Support test campaigns and perform data analysis to characterize the… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design ... for test , floorplanning, place and route, clock methodology, power planning and analysis, timing closure, STA, signal integrity and physical design checks. +… more