- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
- NVIDIA (Santa Clara, CA)
- …power NVIDIA's next generation of AI chips. What you will be doing: + Drive robust methodology for timing analysis of custom circuit IP. + Support SRAM and ... the world! We are currently looking for a SRAM Timing Engineer to join our team of...other custom circuit design engineers through successful timing convergence towards tape-out. + Work closely with design… more
- Cisco (San Jose, CA)
- …high-performance, feature-rich ASICs used in Cisco's networking products and third-party custom -built hardware solutions. Your Impact * Be part of the development ... organization as an ASIC Design Engineer with primary focus on RTL Design * Create...participate in reviews * Implement Verilog RTL to meet timing and performance requirements * Help define, evolve, and… more
- Qualcomm (Santa Clara, CA)
- …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and power… more
- NVIDIA (Santa Clara, CA)
- …with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation...be. What you'll be doing: + Work in NVIDIA's semi- custom engineering team building customized chip solutions targeting data… more
- Cisco (San Jose, CA)
- …Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation using DFT patterns. ... Tcl, Python/Perl. Preferred Qualifications: * Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification *… more