- SpaceX (Irvine, CA)
- …domain crossing paths at block and full chip level + Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon...reliable internet to 3M+ users worldwide. We design, build, test , and operate all parts of the system -… more
- Teradyne (Agoura Hills, CA)
- …reports on the results/findings. The role will involve direct communication with Teradyne's ASIC design team, ATE test team and our internal customers. + ... We are the global test and automation specialists, powering next-generation technologies through...Signal /power integrity experience is preferred. + Experience with mixed signals (analog and digital). + Experience characterizing PLLs,… more
- SpaceX (Irvine, CA)
- …working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in ... reliable internet to 3M+ users worldwide. We design, build, test , and operate all parts of the system -...layout at the technical level, and will work with RFIC/ mixed signal designers on full chip layout… more