- Google (Madison, WI)
- …or PhD in Electrical Engineering or Computer Science. + 4 years of experience in digital/ ASIC design using SystemVerilog or RTL . + Experience in one or ... design architecture and microarchitecture specifications. + Develop SystemVerilog RTL to implement logic for ASIC /SoC products...(DV) teams to create testplans for, verify, and debug design RTL . + Work with physical … more