- Broadcom (Allentown, PA)
- …development, constraints validation, timing analysis and closure. + Experience with formal verification , timing analysis and Eco implementation. + Experience ... clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able to drive tools and...with timing analysis and place and route tools for ASIC / SoC Design is a must. + Should have… more
- Broadcom (Allentown, PA)
- …development, constraints validation, timing analysis and closure. + Experience with formal verification , timing analysis and Eco implementation. + Experience ... placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). + Drive tools and methodologies to achieve desired PPA… more