• Chip Package Signal

    Google (Sunnyvale, CA)
    …hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Signal and Power Integrity Engineer you will be ... responsible for the chip package design with signal / power integrity...team and vendors. You will drive chip packaging signal and power implementations… more
    Google (09/07/24)
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  • Analog/mixed- signal IC Design Engineer…

    Cisco (San Jose, CA)
    …* You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met. Who you'll work with: * You ... plus: Passive component design: inductors, -transformers, transmission-lines, etc. -Floorplanning ( power /ground, digital/analog signal routing, etc.) -Custom transistor… more
    Cisco (08/07/24)
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  • Principal Signal Integrity Engineer - TPG

    Micron Technology, Inc. (San Jose, CA)
    …across multiple disciplines and organizations (eg, Signal Integrity, Circuit and Chip Design, Packaging R&D and System Integration). **Qualifications** + PhD ... in future performance scaling through sophisticated signaling techniques and package / channel improvement, including circuit power ...or MSEE w/10 years of industry experience + Strong Signal and Power Integrity Background + Strong… more
    Micron Technology, Inc. (10/02/24)
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  • RF/Analog Design/Mixed- Signal Engineering…

    Qualcomm (Santa Clara, CA)
    …optimization, RFIC / Analog IC Design, PA architectures, RF Front-End Engineering, Signal Processing/Integration, RF microwave design, power amplifiers, WLAN / ... Amplifiers, Transmitter, Receiver, ACLR + Layout experience and chip tape-out + Programming Experience in Perl, MATLAB, Cadence,...signal IPs + Cadence Design Environment + Low power analog/digital design + Perl, Verilog, Shell, Python, Tcl,… more
    Qualcomm (08/20/24)
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  • Signal Integrity Manager, Platforms…

    Google (Sunnyvale, CA)
    …or equivalent practical experience. + 8 years of experience working in a signal integrity technical environment, or 7 years of experience with an advanced degree. ... the product development process for mass volume production design, with a focus on signal integrity and lab validation. + Experience with SerDes testing in a lab… more
    Google (09/07/24)
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  • Principal Analog/ Mixed- Signal IC Design…

    Cisco (San Jose, CA)
    …component design: inductors, transformers, transmission lines, etc.) * Floorplanning ( power /ground, digital/analog signal routing) * Custom transistor layout ... Who we are Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G...definition and implementation of large-scale block on a complex chip . * You will mentor team members and track… more
    Cisco (08/27/24)
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  • Analog / Mixed- Signal IC Design Engineer…

    Lightmatter (Mountain View, CA)
    Analog / Mixed- Signal IC Design Engineer Lightmatter builds chips that enable extreme-scale artificial intelligence computing clusters. If you're a collaborative ... and location. Responsibilities + Participate in the architecture development with our chip architects by leading feasibility studies + Collaborate with other design… more
    Lightmatter (08/16/24)
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  • 3D IC Solutions Engineer- Package Design…

    Siemens Digital Industries Software (Fremont, CA)
    …) o Package Design Cadence (APD/SiP), Siemens (XSI/XPD) o Signal / Power integrity analysis: Siemens (HyperLynx SI/PI), Ansys (Redhawk, Totem, Swave), ... deliver better products in the increasingly complex world of chip , board and system design. **Job Overview** Siemens EDA...performing individual for an opportunity to serve as the package design lead in our 3D IC Solutions Engineering… more
    Siemens Digital Industries Software (08/25/24)
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  • IC Layout Engineer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …working on multiple silicon projects that are driving more integration, lower power , mixed signal architectures and advanced silicon technology for deployment ... at the technical level, and will work with RFIC/mixed signal designers on full chip layout of...designers and chip leads to determine the chip floor plan; this includes strategies for power more
    SpaceX (09/25/24)
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  • Senior Package Layout Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …pinout incorporating system level trade-offs of pins assignment. + Help perform package routing, placement, stack-up, reference plane and power distribution ... NVIDIA's GPUs and SOCs are the world leaders in power , performance and efficiency. We are continually innovating to...this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a… more
    NVIDIA (08/16/24)
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  • Sr./ Principal Analog Architect

    Lightmatter (Mountain View, CA)
    …solutions. This role requires a deep understanding of high-frequency systems-on- chip (SoCs), high-speed (40+ GHz) electro-optic interfaces, silicon photonics, and ... + Creative problem-solving and owning the architectures, characterization plans, and packaging approaches for a successful high-volume product. + Be the AMS… more
    Lightmatter (08/17/24)
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  • Mechanical Engineering Internship - Summer

    Qualcomm (Santa Clara, CA)
    …within areas of signal integrity, IC packaging , high performance chip / package CPI analysis, power integrity, thermal engineering and more! **Minimum ... Mechanical design, heat transfer, microelectronics device. + Knowledge of IC packaging structures, chip - package , electronic packaging process and … more
    Qualcomm (08/20/24)
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  • SiliconOne Electrical Validation Lead

    Cisco (San Jose, CA)
    …be cooperating with various groups across the globe such as: Board-Design, Software, Signal and Power Integrity, Packaging and Production. Minimum ... Switch ASIC Post-Silicon Electrical Validation. You will deal with all chip validation aspects: Building validation plan, Coding the validation SW environment… more
    Cisco (07/25/24)
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  • Senior Failure Analysis Engineer (Automotive)

    Power Integrations (San Jose, CA)
    …for external customers. Experience & Requirements: + Experience in failure analysis of power semiconductors, analog, and/or mixed signal IC devices. + Experience ... Power Supply applications, and analog, and/or mixed signal integrated circuit devices. + Fluent verbal, read, and...and the ability to apply fault isolation techniques at chip level as well as PCB at power more
    Power Integrations (07/10/24)
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  • Staff RF SiP Module Design Engineer

    Skyworks (San Jose, CA)
    …analog/digital & RF semiconductors, Acoustic Filters and integrating ultra dense System-In- Package solutions that will be powering the next wireless transformation. ... Houses/Smart Cities through IoT, and the AI/ML revolution. Through our broad technology/ packaging expertise and one of the most extensive product portfolios in the… more
    Skyworks (09/10/24)
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  • Principal Software Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …hardware design, analysis, and verification. + Collaborate with cross-functional teams, including chip , package , board products, and IP teams, to define ... development experience, ideally in EDA simulation, with a focus on signal / power integrity, channel simulation, and high-speed standards (DDR and SerDes). +… more
    Cadence Design Systems, Inc. (10/01/24)
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  • ASIC Design Engineer, Cloud-Scale Machine Learning…

    Amazon (Cupertino, CA)
    …to Global 500 companies trust our robust suite of products and services to power their businesses. Diverse Experiences AWS values diverse experiences. Even if you do ... develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning...multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing - As a key member of the… more
    Amazon (07/25/24)
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  • Principal Switch Engineering Architect

    NVIDIA (Santa Clara, CA)
    …and package design to understand the different design limitations: power , di/dt, temperature, signal -integrity etc. + Thoroughly understand Ethernet, ... define the POR of our switch product line. + Face the most challenging Full- Chip correctness and performance issues, which cannot be handled by the units' designers… more
    NVIDIA (08/16/24)
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  • RF Module Engineer

    Skyworks (San Jose, CA)
    …team of EM Design Engineers, Lab Technicians, Verification Engineers, Test Engineers and Package Engineers to tackle complex cellular RF front end issues + Prepare ... + Familiar with lab instruments including Network Analyzers, Spectrum Analyzers, Signal Generators, RF Probe Stations, Noise Figure Analyzers and Load-pull Tuners… more
    Skyworks (08/14/24)
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  • Assistant Professor - Electrical Engineering:…

    San Jose State University (San Jose, CA)
    signal processing, network and network security, mobile network, power electronics, energy systems, microprocessors and computer systems, embedded systems, ... Summary (https://www2.calstate.edu/csu-system/careers/benefits/Documents/employee-benefits-summary.pdf) for details about the CSU's excellent benefits package . Target Start Date: August 18, 2025 Application Deadline:… more
    San Jose State University (08/22/24)
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