- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- Capgemini (San Jose, CA)
- **Job Role : Senior RTL Engineer** **Job Location : San Jose CA** **Job description:** We are seeking RTL Engineer with experience in sigma-delta ADC. **Key ... responsibilities:** Engineer will be working on RTL Blocks and will be involved in writing ...fundamentals in VLSI design. + Strong problem-solving and data analysis skills. + Strong skills using scripting languages such… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Cisco (San Jose, CA)
- …fullchip timing in multiple timing modes. * Option to also do block level RTL design or block or top-level IP integration. * Helping develop efficient methodology ... back to block level. * Helping develop and apply methodology to ensure correctness and quality of SDCs as...block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. * Leading the… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer, you will contribute to all design ... subchip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry...and final physical verification. + Good knowledge of timing analysis , power analysis , physical verification (DRC/LVS), and… more
- Cisco (San Jose, CA)
- …and power requirements. * Contribute to full chip integration and timing methodology / analysis . * Develop and analyze functional coverage. * Help define, ... evolve, and support our design methodology . * Collaborate with the verification team to address design bugs and close code coverage. * Work closely with the physical… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Qualcomm (Santa Clara, CA)
- …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and ... IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and… more