- Meta (Sunnyvale, CA)
- …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design implementation ... logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology… more
- Cisco (San Jose, CA)
- …high-performance, feature-rich ASICs used in Cisco's networking products and third-party custom -built hardware solutions. Your Impact * Be part of the development ... organization as an ASIC Design Engineer with primary focus on RTL Design * Create...participate in reviews * Implement Verilog RTL to meet timing and performance requirements * Help define, evolve, and… more
- Meta (Sunnyvale, CA)
- …Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop cutting-edge AMS ... optimize state-of-the-art AMS IP's, while also supporting the development of next-gen custom mixed signal IC's for our industry-leading virtual and augmented reality… more
- Amazon (Sunnyvale, CA)
- …an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of ... the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design… more
- Qualcomm (Santa Clara, CA)
- …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and power… more
- Google (Sunnyvale, CA)
- …speed serdes. + Familiarity to next generation memory and chiplet standards and timing budget methodology . + Excellent programming and data analysis skill with ... with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams. + Experience with 2.5D/3D… more
- Google (Mountain View, CA)
- …low-power design techniques. + Experience with ARM-based SoCs, interconnects and ASIC methodology . + Experience with a scripting language like Python or Perl. ... interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with methodologies for RTL quality… more