We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Qualcomm (Santa Clara, CA)
- …digital transformation to help create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers, implementation ... engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and...using Verilog or VHDL + Experience with ASIC test, DFT , and debug + 5+ years of practical experience… more
- Broadcom (San Jose, CA)
- …San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you ... our HBM, DDR and SerDes designs through comprehensive Design for Test ( DFT ) verification strategies. You will work collaboratively with cross-functional teams to… more
- Meta (Sunnyvale, CA)
- …DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT strategies for ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work...our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and verification to build best-in-class System… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most ... network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. .… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow...You'll Do * Responsible for implementing the Hardware Design-for-Test ( DFT ) features that support ATE, in-system test, debug and… more
- Capgemini (Santa Clara, CA)
- **Location: San Clara, California.** **Job description:** The RTL Engineer performs detailed block design from system requirements and evolving specifications. ... creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals.… more
- NVIDIA (Santa Clara, CA)
- …characterization problems. + Cross functionally lead efforts with design, foundry, DFT , test, Planning and quality to root-cause and solve technical problems. ... characterization and qualification. + Knowledgeable in ATE test flows, DFT and device physics. + Proficient in statistical data...industry's best employers. If you're a creative and autonomous engineer with a real passion for technology, we want… more
- Google (Sunnyvale, CA)
- …product engineering. + Experience in Application-Specific Integrated Circuit (ASIC) or SoC DFT test development, bring-up, or debug for NPI prototypes or High Volume ... cross-functional teams. + Own IP-level test development for Design for testing ( DFT ) structural tests, functional tests, or eFuse programming. + Support Chip-level … more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...crossing (CDC) logic + Exposure to Design For Test ( DFT ), understanding of scan and writing DFT … more
- NVIDIA (Santa Clara, CA)
- We are looking for a creative ATE Test Development Engineer . NVIDIA has continuously reinvented itself for three decades. Our invention of the GPU in 1999 fueled the ... + Actively participate with multi-functional teams including Product Development Engineering, DFT , and IC design to efficiently debug product failures and implement… more
- NVIDIA (Santa Clara, CA)
- We are looking for a creative and experienced ATE Test Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... + Actively participate with multi-functional teams including Product Development Engineering, DFT , and IC design to efficiently debug product failures and implement… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Product Development Engineer to join our outstanding Automotive/Embedded Systems team! As part of an Operations Engineering team that ... Experience with ASIC mixed-signal design, characterization and qualification + Knowledgeable in DFT and device physics + Proficient in statistical modeling of data… more
- Amazon (Sunnyvale, CA)
- …the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design ... SoCs tested on Teradyne and Advantest equipment. Convert test patterns from the DFT team into tester-suitable formats (eg ATP). Run test vectors on test platforms… more
- Broadcom (San Jose, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... resident expert in areas such as physical design, STA, DFT , and packaging? Have you taped out so many...logic design verification, DRC, logic synthesis 4. Knowledge of DFT methods including scan, boundary scan, memory BIST and… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow...physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: * Perform full… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
- Cisco (San Jose, CA)
- …designs, custom library development (Standard Cell and I/O), physical design & DFT , Signal Integrity, and complexed packaging technology. Our silicon is developed ... processing, high-speed logic design & verification, memory designs, and physical design & DFT . Why Cisco #WeAreCisco, where each person is unique, but we bring our… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of hard-working ... need to see: + BS (or equivalent experience) in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD) a plus. + 3+ years… more