We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Qualcomm (Santa Clara, CA)
- …to understand the HW u-architecture of the infrastructure components involved, the memory system and interconnect, identify performance bottlenecks; define ... are implemented in all Qualcomm SoCs. This position primarily involves studying System Performance using cycle-accurate/approximate models and support both Infra… more
- NVIDIA (Santa Clara, CA)
- …in a related hardware engineering role. + Deep understanding of memory sub - systems as used in high- performance computing, including DDR/5/6, LPDDR4/5/6, ... improvements to advanced DDR and LPDDR technologies and the systems built using them to balance performance ,...to Nvidia product segment goals. You will work with memory system architects and external vendors to… more
- Meta (Sunnyvale, CA)
- …as volatile memory , memory management and its impacts on overall system performance 24. Experience with AR/MR or systems aimed at ... lead the definition and convergence of complex and novel sub - systems , and product architectures aimed at pushing...programming, computer vision, OS, game development and complex sensing systems 22. Experience modeling system power and,… more
- Google (Mountain View, CA)
- …and require balancing between Performance , Latency, and Power in MCU, SoC, Memory , RF, or other sub - systems . Preferred qualifications: + PhD in ... or developing hardware platforms or system features for consumer wearable systems . + Experience in developing performance , latency or power modeling tools.… more
- Qualcomm (Santa Clara, CA)
- …and scalable architectures across key technologies including heterogenous compute, memory systems , interconnects, multimedia, AI/ML, multi-die, power-management ... (micro-architecture) + Demonstrated deep technical knowledge and achievements at the SoC, sub - system or large IP levels as micro-architect or architect +… more
- Microsoft Corporation (Sunnyvale, CA)
- …from conception to microarchitecture specification to post-silicon validation. + Understanding of memory and interconnect sub - systems . + Experience in ... and software teams across Microsoft to identify opportunities to improve system power and performance management with a goal of improved power efficiency across… more
- Meta (Sunnyvale, CA)
- …Meta. 8. MSEE/CS or equivalent experience 9. Understanding of SoC Architecture, NoCs, memory sub - system , Quality of Service (QoS), and heterogeneous compute ... principles. 10. Experience with SoC/IP/ System performance modeling and correlation 11. Understanding of basic power concepts and trade-offs 12. Experience in… more
- NVIDIA (Santa Clara, CA)
- …+ High-level understanding of Computer Architecture -- CPUs, GPU, AI accelerator, Fabric, Memory Sub System , Networking. + Workload analysis and ... a plus + Understanding of the many factors influencing performance and power at chip, system , and product levels. + Excellent coding and algorithmic thinking… more
- Microsoft Corporation (Sunnyvale, CA)
- … and power metrics. You will be a key contributor, performing power analysis at sub system level and collaborating with other architects in WSSI and the Surface ... As a vital member of the **Windows Silicon and Systems Integration (WSSI)** Team, The **Competitive Analysis SoC Architect**...SoC Architect** will be responsible for researching power and performance across a variety of devices, workloads and use… more
- Applied Materials (Santa Clara, CA)
- …continuous demands for scaled devices, denser interconnects that significantly improves the system Power, Performance and Area. + Your primary responsibility ... emerging memory especially DRAM and future 2nm technologies (deep sub -submicron FET architectures, including nanowires and Finfet). You will also be developing… more
- Broadcom (San Jose, CA)
- …design backend flows, help define and influence sub - system content for memory interfaces, NOC, processor sub - systems et al. The individual will also ... manufacture of the ASIC with emphasis on low power, optimized area, max. performance and high overall manufacturing yield. The candidate should have a strong… more
- Amazon (Cupertino, CA)
- …- Have familiarity with key components such as interconnects, DMAs, Memory sub - systems , accelerator engines, debug and system level architectures - Have ... and Japan, and customers across all industries. Custom SoCs ( System on Chip) live at the heart of AWS...ASIC Design Engineer, you will: * Develop and implement high- performance , area and power-efficient RTL designs to meet project… more
- Google (Mountain View, CA)
- …use cases and applications, and how they relate to specific hardware blocks or sub - systems . You will represent the goals of the software team, their asking ... computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems. + 5 years of C or C++...in the area of consumer electronics or other embedded systems . + 3 years of experience in driving ASIC… more
- Broadcom (San Jose, CA)
- …& customers and is responsible for developing cost effective high performance , advanced custom package solutions achieving signal integrity, thermal, structural ... & qualification; program management with external assembly partners -Lead in memory supplier(s) engagement to define technology and quality requirements. -Interface… more
- NVIDIA (Santa Clara, CA)
- …such as Cadence virtuoso. + Optimize circuit to meet the specifications for system performance . + Work with layout engineers by providing detailed floorplan ... team building next generation High Speed IOs for GDDR/HBM Memory Interfaces. This position offers the opportunity to have...Analog / Mixed Signal Circuit Design Experience in deep sub -micron process (especially in FINFET). + Experience with design… more
- NVIDIA (Santa Clara, CA)
- …such as Cadence virtuoso. + Optimize circuit to meet the specifications for system performance . + Work with layout engineers by providing detailed floorplan ... team building next generation High Speed IOs for GDDR/HBM Memory Interfaces. This position offers the opportunity to have...Analog / Mixed Signal Circuit Design Experience in deep sub -micron process (especially in FINFET). + Experience with design… more
- NVIDIA (Santa Clara, CA)
- …Network protocol, internal/external enterprise storage devices, PCIe buses and devices, IO sub -devices, CPU and memory , ACPI, UEFI spec, Redfish - huge ... stack from design doc. + Installing and testing various systems OS, server firmware and SW stack. + Drive...+ Ability to write test plans focusing on functional, performance , stress and negative testing. + Experience in developing… more