We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring ... including key stages like floorplanning, place and route, and timing closure). + Experience in Python, Tcl, or Perl...architecture and its integration within AI/ML-driven systems. As an ASIC Physical Design Engineer , you will collaborate… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. +… more
- SpaceX (Sunnyvale, CA)
- …to work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer / Senior : $210,000.00 - $280,000.00/per year Your actual ... Principal ASIC Design Engineer (Silicon Engineering) Sunnyvale,...that in top level and deliver the fully verified, synthesis/ timing clean design + Work closely with verification team… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Strong familiarity and experience with all stages of ASIC design flow including front end design and verification,...flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding interpersonal… more
- Palo Alto Networks (Santa Clara, CA)
- …and the kind of precision that drives great outcomes. **Your Career** Join our ASIC team and help deliver the digital logic that powers our next-generation firewall ... and add design-for-debug features. + **Partner** with physical-design teams: review synthesis/ timing reports, rewrite RTL to close critical paths, and consult on… more
- Amazon (Sunnyvale, CA)
- …Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer , you will be part of an advanced design and ... in design methodologies and EDA tools - Experience working with Synthesis, timing closure, and design constraints Preferred Qualifications - Experience with ARM and… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more
- NVIDIA (Santa Clara, CA)
- …NICs, Switches on standard FPGA prototyping platforms. We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa ... Are you passionate about DGX system connecting multiple ASIC chips together and FPGA prototyping? Are you...and route. + Improve performance of the prototype, analyze timing and generate bit streams. + Bring up the… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate ... preferred. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test...of JTAG 1149.1/6, IEEE1500 and IEEE1687 + Knowledge of timing analysis and equivalency checks would be added bonus… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... in a dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit. What we need to see:...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... in a dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit. What we need to see:...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Cisco (Milpitas, CA)
- …features. **Your Impact** We are seeking a highly experienced and accomplished FPGA Senior Design Engineer to provide technical leadership and deep expertise in ... the entire FPGA tool flow, including synthesis, placement, routing, and static timing analysis. Aggressively pursue timing closure to meet strict performance… more
- Microsoft Corporation (Mountain View, CA)
- …for passionate engineers to help achieve that mission. We are looking for a ** Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence ... 5+ years of experience delivering successful IP or Application Specific Integrated Circuits ( ASIC )/SOC designs. + 4+ years of experience in Synthesis, Timing … more