We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- Amazon (Cupertino, CA)
- …integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, ... physical design work. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies. Be able to independently… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS...GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS...or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing… more
- Amazon (Sunnyvale, CA)
- …un-served and under-served communities around the world. Come work at Amazon! As Senior RF ATE Engineer , you will engage with an experienced cross-disciplinary ... collaborative peer environment. You'll be responsible for RFIC high-volume production test methodology of mm-wave RFICs for Amazon Leo custom silicon. You'll be part… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- Microsoft Corporation (Mountain View, CA)
- …engineers so that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the development and adoption of ... curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and… more
- SpaceX (Sunnyvale, CA)
- …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base ... Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was...sequential pipeline planning and top level design for testability ( DFT ) planning + Collaborate with chip architects, ASIC engineers,… more