We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
- Microsoft Corporation (Sunnyvale, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Power and Performance Engineer** to join the team. **Responsibilities** + Work with ... power efficiency across the stack. + Develop power and performance modeling methodology by creating and owning System on Chip (SOC) architectural power models.… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Qualcomm (Santa Clara, CA)
- …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and ... their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon… more