We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Capgemini (Santa Clara, CA)
- …US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Sr. Logic Design ( RTL ) Engineer_ **Location:** _CA-Santa Clara_ ... **Location: San Clara, California.** **Job description:** The RTL Engineer performs detailed block design ...description:** The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform … more
- Capgemini (San Jose, CA)
- …**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Logic Design ( RTL ) Engineer_ **Location:** _CA-San Jose_ **Requisition ... **Job Role : Senior RTL Engineer** **Job Location :...or related field. + 10 years of experience in Logic ( RTL ) Design , SystemVerilog, Verilog/VHDL,… more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages ... such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code,...this role, you will be responsible for Register-Transfer Level ( RTL ) design development of camera and machine… more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages ... such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code,...Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …includes but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong ... and developing flows at all phases of the digital design and functional verification. It is further expected that...the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered. Position… more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages ... with an emphasis on computer architecture. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as… more
- MetaOption, LLC (Milpitas, CA)
- …meet product Performance-Power-Area-Schedule requirements. Tasks may include Architecture / micro-Architecture; Logic Design ; RTL integration and coding; ... Sr . Front-End ASIC Design Engineer Candidate needs SoC/ASIC experience working hands on currently, with non-off the shelf designs. - Compute (ie, CPUs), memory… more
- NVIDIA (Santa Clara, CA)
- …with industry-standard tools. Deep understanding of hardware architecture and hands-on skills in RTL / logic design for timing closure. + Experience in ... We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing...equivalent experience) with 2 years' experience. + Expertise in logic equivalence checking/FV required from RTL to… more
- NVIDIA (Santa Clara, CA)
- …improving PPA (Performance, Power, Area). + Good understanding of hardware architecture and RTL / logic design for timing closure, specifically experience in ... + Work in a cross-functional environment interacting with multiple teams, including Architecture and RTL team, to solve complex design problems as well as build… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join...Boot controllers. + You will be responsible for the RTL design , logic synthesis, and ... design concepts and experience in ASIC design flow including RTL design , verification, logic synthesis and timing analysis + Strong coding skills in… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the ... deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for...logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification… more
- NVIDIA (Santa Clara, CA)
- …networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis and timing analysis. + Exposure ... We are now looking for a Senior ASIC Design Engineer. NVIDIA is...document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.… more
- Belcan (Palo Alto, CA)
- Sr . Physical Design Engineer Job Number:...address timing, congestion and power issues. In-Depth Knowledge of design flow from RTL to GDSII. Good ... 354330 Category: Design Engineering Description: Job Title: Sr . Physical Design Engineer Pay rate: $66.34...chip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry… more
- NVIDIA (Santa Clara, CA)
- …years in a leadership role + Expertise in Verilog or SystemVerilog, logic design , and circuit modeling in RTL for mixed-signal blocks + Strong background in ... Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL / design … more
- Broadcom (San Jose, CA)
- …nice to have:** + Exposure to SERDES communications protocols. + Logic design , chip architecture, microarchitecture, Verilog RTL coding Front-end logic ... Candidate Account, please Sign-In before you apply.** **Job Description:** ** Senior Custom ASIC Engineering Lead** Are you a versatile,...in physical design and STA, EDA tools, design flows for physical design , logic… more
- Amazon (Cupertino, CA)
- …making the right trade-offs. Key job responsibilities - Work with RTL / logic designers to drive architectural feasibility studies, explore power-performance-area ... team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL... design engineers as well as with the RTL /Arch. teams About the team Inclusive Team Culture Here… more
- NVIDIA (Santa Clara, CA)
- …silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis, timing analysis and bringup. + ... We are now looking for a Senior Design for Debug (DFD) Architect...bus protocols, interconnect networks and/or caches. + Expertise in design for debug techniques and methodologies, integrated logic… more
- Amazon (Sunnyvale, CA)
- …and DFT teams to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work ... lead you will set up the flow for both logic and physical synthesis flow for various technology nodes....experience in ASIC implementation. * Experience in leading physical design . * Strong exposure to UPF flow for low… more
- NVIDIA (Santa Clara, CA)
- …a dedicated and motivated Software developer with particular interest in algorithms and RTL Design . Understanding both Software and Hardware principles will be a ... + Improve algorithms (in C++) for automated connectivity, auto logic insertion and post processing Verilog RTL ...stand out from the crowd: + Prior experience in RTL design (Verilog), verification and synthesis. +… more