• Sr. SOC/ ASIC DFT Engineer

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
    SpaceX (12/16/25)
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  • ASIC /SOC DFT Engineer

    SpaceX (Sunnyvale, CA)
    ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... this possible, with the ultimate goal of enabling human life on Mars. ASIC /SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
    SpaceX (09/18/25)
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  • DFT Quality Engineer

    Broadcom (San Jose, CA)
    …already have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** DFT Quality Engineer ** Broadcom's ASIC Product Division is ... seeking candidates for a DFT Quality Engineer position at our San Jose design center in...for test/yield optimization (outlier analysis, etc)_ + Ensure Broadcom ASIC Product Division understands the test industry -- test… more
    Broadcom (12/12/25)
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  • HBM/DDR/SerDes DFT Verification Lead…

    Broadcom (San Jose, CA)
    …San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you ... Account, please Sign-In before you apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead… more
    Broadcom (12/06/25)
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  • Senior DFT Static Timing Analysis…

    Google (Sunnyvale, CA)
    Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... timing analysis and timing ECO creation, timing margins). + Experience in DFT architectures and associated test methodologies. + Experience in Tessent generated … more
    Google (12/05/25)
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  • Senior Principal DFT Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and ... preferred. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT more
    Cadence Design Systems, Inc. (10/30/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You ... you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most… more
    Broadcom (11/19/25)
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  • Senior ASIC Engineer - SDC

    Cisco (San Jose, CA)
    **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
    Cisco (12/03/25)
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  • Senior ASIC Design Engineer - DFX

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the… more
    NVIDIA (10/25/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact on physical design… more
    SpaceX (12/16/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
    SpaceX (12/16/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/ DFT /LEC/STA) + Partner and work with back-end team until chip tape-out. +… more
    NVIDIA (11/26/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a group of ... to see: + MS/Phd in Electrical Engineering or Computer Engineer or related degree (or equivalent experience). + 5+...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT ,… more
    NVIDIA (12/13/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to have real ... or Computer Engineering. + 5+ years of proven experience working on ASIC design and development. + Experience in micro-architecture and RTL development of… more
    NVIDIA (12/10/25)
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  • Sr. ASIC Design Engineer

    Amazon (Cupertino, CA)
    …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/ DFT signal routing - As a key member of...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
    Amazon (11/20/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
    NVIDIA (12/10/25)
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  • Senior ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... GPUs or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan shift and… more
    NVIDIA (11/22/25)
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  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... lint and work w/ designers to create waivers. 6. Perform RTL DFT analysis and improve DFT coverage for stuck-at faults. 7. Perform flat and hierarchical clock… more
    Meta (09/20/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...implementing Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most… more
    NVIDIA (12/10/25)
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  • ASIC Clocks Design Engineer - New…

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for an outstanding ASIC engineer to join the team. The Team is responsible for crafting all aspects ... to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in end-to-end cycle of... teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes,… more
    NVIDIA (12/10/25)
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