- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... to optimize performance, yield, and reliability through increasingly comprehensive modeling , informative analysis, and automation. This work will influence the… more
- Google (Mountain View, CA)
- …and post-silicon tuning for power and performance. + Experience with ASIC power modeling /estimation, defining power targets, power roll-ups, ... memory subsystems. + 5 years of experience in SoC power management or low power design/ methodology . + Experience with Application-Specific Integrated Circuit… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... creative Signal Integrity solutions to complex system design problems. + Modeling and Optimization of vias, connectors, sockets, breakouts and various system… more
- LinkedIn (Sunnyvale, CA)
- …York), India and Dublin. We leverage science and engineering to maximize the power of data. Our work spans member engagement, growth, marketing, sales, operations, ... by the business needs of the team. As the Senior Manager of Data Science for the PSM (Product...as define where to build scalable technology and aligned methodology across lines of business. * Build strong collaboration… more
- Palo Alto Networks (Santa Clara, CA)
- …- just to name a few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full ... of Palo Alto Networks Firewall and SD-WAN hardware including: selecting components; modeling and simulating memory and serdes interfaces; modeling PDN networks;… more
- NVIDIA (Santa Clara, CA)
- …up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience ... to improve timing convergence flows working with the methodology teams. What we need to see: + BS...of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes. Ways to… more
- NVIDIA (Santa Clara, CA)
- …closure of high-performance designs with a focus on improving PPA (Performance, Power , Area). + Good understanding of hardware architecture and RTL/logic design for ... Timing. + Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging high-performance designs in these nodes. Ways to stand out… more