- Google (Sunnyvale, CA)
- …benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) . + Own timing constraint creation and validation, perform timing ... experience. + 5 years of experience in the domain of static timing analysis. (ie, constraint authoring and verification, static timing analysis and timing… more
- Amazon (Cupertino, CA)
- …fundamentals - 1+ years doing Static Timing Analysis - 1+ years with timing constraint development - Timing Analysis using EDA tools (examples: ... our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud...and leads. * Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).… more
- Cisco (San Jose, CA)
- … Analysis. * Experience with constraint analyzer tools such as Fishtail/TCM ( Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint ... from concept to first customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- Broadcom (San Jose, CA)
- …debugging, and coverage closure + Collaborate with physical design team on constraint generation, timing closure analysis, formal verification, low power checks ... design and validation techniques including UPF/CPF Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset… more
- Capgemini (Santa Clara, CA)
- …and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and ... **Location: San Clara, California.** **Job description:** The RTL Engineer performs detailed block design from system requirements… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the ... part of a world-class engineering team. **Required Skills:** ASIC Package Engineer SI/PI Responsibilities: 1. Drive chip-package-system co-design by driving signal… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal Integrity Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... tool/methodology. + Package substrate and board layout SI design constraint creation, review with pre/post layout SI + Opportunity...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding of fundamental physical ... design flows and stages + Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. + Exhibit excellent communication skills and be self-motivated and well organized. + Experience with FPGA and/or emulation… more
- NVIDIA (Santa Clara, CA)
- …complete development of PCB layout, floor planning and detailed component placement, constraint management, with a concept of topology and signal/trace integrity. + ... a plus. + Knowledge of PCB design and consideration for layout, routing, and timing constraints, DFM, DFA, and DFT constraints in volume manufacturing is helpful. +… more