- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** ... more
- Cisco (San Jose, CA)
- …Who You'll Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate ... more
- Cisco (San Jose, CA)
- …* Bachelor's Degree in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification ... more
- Cisco (San Jose, CA)
- …Qualifications * Bachelor's Degree in EE, CE, or other related field with 5+ years of ASIC design verification experience. * 5+ years of related ASIC ... more
- Broadcom (San Jose, CA)
- …power efficiency._** **_We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can ... more
- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed in the industry. What You'll Do As ASIC Verification Engineer in The Core Hardware Business Unit, you will be ... more
- Cisco (San Jose, CA)
- …the ASIC in deployment-mode applications. Your Impact You will participate in the ASIC design verification for Cisco high-end switching Products, one of ... more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... more
- Cisco (San Jose, CA)
- …* Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering ... more
- Cisco (San Jose, CA)
- …ASICs being developed in the industry. Your Impact You will collaborate with architects, ASIC front-end and Design Verification teams to understand chip ... more
- Cisco (San Jose, CA)
- …* Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience. * Verilog/System Verilog programming experience. * Interactive ... more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... more
- Meta (Menlo Park, CA)
- …applications. The role also involves partnering with Full Stack Software, Hardware, ASIC Design , Verification , Emulation, Pre/Post-Silicon Validation & ... more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... more
- Cisco (San Jose, CA)
- …and be responsible for ASIC bring up Minimum Qualifications: * 7+ years ASIC design verification experience with a bachelor's or master's degree * ... more
- Cisco (San Jose, CA)
- …custom-built hardware solutions. Your Impact * Be part of the development organization as an ASIC Design Engineer with primary focus on RTL Design ... more
- Meta (Menlo Park, CA)
- …the architecture. 4. Work with a broad array of cross functional partners in ASIC design , verification , silicon bring-up, firmware and software development ... more
- Cisco (San Jose, CA)
- …* Be responsible for ASIC bring up Minimum Qualifications * 8+ years ASIC design verification experience with Bachelor's or Master's degree in equivalent ... more