- Cadence Design Systems, Inc. (San Jose, CA)
- …the world of technology. Provide technical support and customization of timing closure , analysis and ECO flows; spanning digital block, die and 3DIC ... adoption and proliferation of Cadence tools and technologies Requirements; 10+ years timing closure , analysis and ECO flows; spanning digital block, die and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …or related field 8+ years of design/EDA experience Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is ... backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure Experience in scripting languages such as… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …+ 5+ years industry related experience in the following. + Expertise in Timing Signoff/Extraction/EMIR for both block/full chip closure + Prefer experience with ... and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post-sales… more
- Microsoft Corporation (Mountain View, CA)
- …of experience in RTL-to-GDS tasks such as floorplanning, bump planning, synthesis, timing closure , place-and-route, electromigration & voltage drop, and physical ... everyone can thrive at work and beyond. **Responsibilities** + ** Principal Physical Design, responsible for:** + Providing technical direction...: + **Soft IP Projects** : Ensure IPs meet timing , power, and area targets. + **Test Chips** :… more