• Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …who want to make an impact on the world of technology. Job Title: Principal Product Engineer Location: San Jose, CA Reports to: Product Engineering Director Job ... verification languages and methodologies like SystemVerilog, VHDL, C/C++ UVM, ' e ' + Experience and understanding of client/server technologies, database… more
    Cadence Design Systems, Inc. (11/13/24)
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  • Principal Product Engineer - Verisium Debug

    Cadence Design Systems, Inc. (San Jose, CA)
    …and verification languages and methodologies like SystemVerilog, VHDL, C/C++ UVM, ' e ', UPF, SystemC, SVA. + Experience and understanding of client/server ... company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and… more
    Cadence Design Systems, Inc. (11/23/24)
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