- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
- Cisco (San Jose, CA)
- …to address design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, ... Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering with 4+… more
- Capgemini (San Francisco, CA)
- **Job Role:** ** Physical Design (Synthesis) Engineer** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:**… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer, the ideal candidate will be responsible for ... some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market over the last...power EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing… more
- Broadcom (San Jose, CA)
- …that keep the globe connected. Our ASIC products division is looking for senior , physical design engineering veterans to guide teams designing some of ... Sign-In before you apply.** **Job Description:** Technical Lead for Physical Designs Are you a versatile, senior ...Well verse in EDA tools for physical design verification and sign-off. 6. Knowledge of ASIC… more
- Teledyne (Mountain View, CA)
- …of integrated circuits and related development. Participates in all phases of physical design , including floor planning, clock synthesis, timing optimization, ... + Schematic capture + Circuit simulation + Layout and physical design + Debug and verification for...service issues + Advanced level experience with digital and ASIC design + Advanced level experience with… more
- Capgemini (San Jose, CA)
- **Job Role: Senior ** **Performance Modeling Engineer** **Job Location: San Jose CA** **Job description:** We are seeking a highly skilled candidate with a strong ... candidate will have a deep understanding of System-on-Chip (SoC) design and architecture, as well as Expertise in performance...+ Experience with Synopsys or Cadence EDA tools and ASIC /SOC Power Analysis Tools. + Deep understanding of SoC… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. . Minimum of 5 years in Sales Pursuit Management. ... needs aligned with customer product roadmaps. . Engage with senior management levels to strategize pursuits, develop account maps,...foundries, EDA companies, and IP providers. . Background in ASIC Design or Semiconductor Technology R&D is… more
- Siemens Digital Industries Software (Fremont, CA)
- … with High-Level Synthesis or traditional RTL synthesis + Direct hands-on ASIC or FPGA hardware design experience targeting algorithmic applications such ... nationally, and internationally This role requires a strong digital hardware engineering design & architecture background, with exposure to verification as a plus.… more
- Microsoft Corporation (Mountain View, CA)
- …performance monitors and post-silicon SOC power and performance tuning. + Familiarity with ASIC power analysis, low power design and power optimization. + ... at work and beyond. **Responsibilities** + Work with business, architecture, and design teams to understand power and performance requirements and collaborate across… more