- Cadence Design Systems, Inc. (San Jose, CA)
- …for front-end coding, scripting and developing flows at all phases of the digital design and functional verification . It is further expected that the candidate ... + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP integration and verification + Familiar… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer, the ideal candidate will be responsible for the ... . Physical implementation of blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. . Static and dynamic… more
- City and County of San Francisco (San Francisco, CA)
- …minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Principal Information Systems Engineer - Networks Specialty are only accepted ... systems together as an enterprise networking backbone. The 1044 Principal Networks Engineer is the highest level in the...analytical tasks. Positions at this level are distinguished from Senior IS Engineers, in that the latter performs more… more
- City and County of San Francisco (San Francisco, CA)
- …qualifications. Application Deadline: Continuous How to Apply: Applications for Principal Information Systems Engineer - Applications Specialty are only accepted ... systems together as an enterprise networking backbone. The 1044 Principal Applications Engineer is the highest level in the...analytical tasks. Positions at this level are distinguished from Senior IS Engineers, in that the latter performs more… more
- City and County of San Francisco (San Francisco, CA)
- …of the WWE Business Strategy and Performance Manager, the 1824 Principal Administrative Analyst-Employee Performance & Engagement is responsible for all employee ... measurement tools to track employee performance and reporting out metrics to senior management. 6. Manages and oversees the annual performance planning and review… more
- Qualcomm (San Jose, CA)
- …degree in Science, Engineering, or related field and 4+ years of ASIC design , verification , validation, integration, or related work experience. OR Master's ... Engineering, or related field and 3+ years of ASIC design , verification , validation, integration, or related work...of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal… more
- City and County of San Francisco (San Francisco, CA)
- …Francisco Police Department (SFPD), Technology Division is seeking to hire a Web Developer, Senior IS Programmer Analyst - SFPD (1063) who has a web background in ... Drupal Development and Design . As a member of the Web Team, this...Team, this position is under the direction of the Principal Web Programmer Analysts, where you will be a… more
- Google (Fremont, CA)
- …full-chip assembly, silicon bring-up and correlation, and leading some full-chip design / verification activities. Google's Raxium display group has established a ... field, or equivalent practical experience. + 10 years of experience in analog design fundamentals including circuit design and analog module development from… more
- San Jose State University (San Jose, CA)
- …via the search firm* Reporting to the Provost, the Dean serves as the senior administrator and is the principal champion for vision, leadership, and strategic ... - eg, artificial intelligence (AI), machine learning, human-computer interaction, UI/UX and design - are intersecting with the changing world of information and data… more