- Cadence Design Systems, Inc. (San Jose, CA)
- …an impact on the world of technology. Provide technical support and customization of timing closure, analysis and ECO flows; spanning digital block, die and 3DIC ... proliferation of Cadence tools and technologies Requirements; 10+ years timing closure, analysis and ECO flows; spanning digital... timing closure, analysis and ECO flows; spanning digital block, die and 3DIC methodologies; for complex and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …enable static and dynamic transistor level analysis of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets. Must ... EDA tools and one or more of transistor level timing , power, noise, aging, reliability, and emir analysis +...Enhancing and expanding the existing tools' architecture to cover timing analysis + Creating new frameworks for analysis of… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for front-end coding, scripting and ... developing flows at all phases of the digital design and functional verification. It is further expected...checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint… more
- Qualcomm (San Jose, CA)
- …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties & Responsibilities:** ... a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer, you will define, model, design, optimize,...flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for… more