• ASIC Design Efficiency

    NVIDIA (Santa Clara, CA)
    We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... to extend the state of the art performance and efficiency . + Understand the design and implementation,...art performance and efficiency . + Understand the design and implementation, develop methodology and infrastructure to drive… more
    NVIDIA (11/17/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design ...expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency more
    NVIDIA (12/11/24)
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  • Sr. ASIC Design Verification…

    Qualcomm (Santa Clara, CA)
    …a closely related field is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + ... , Computer Engineering, or a closely related field + 5+ years of experience with ASIC design and verification tools, techniques, and methodology + 5+ years of… more
    Qualcomm (10/14/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... Systems design . + A deep understanding of ASIC design flow including RTL design...virtual channels. + Interest or have prior experience in efficiency enhancement, such as, flow development and code generator.… more
    NVIDIA (11/05/24)
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  • ASIC Design Verification…

    Qualcomm (Santa Clara, CA)
    …This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification ... Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design , verification, validation, integration, or related work experience. OR… more
    Qualcomm (11/21/24)
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  • ASIC Design Verification Staff…

    Qualcomm (Santa Clara, CA)
    …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR ... and emulation strategies) to continuously push the quality and efficiency of test benches + Successful candidate will be...Science, Engineering, or related field and 3+ years of ASIC design , verification, validation, integration, or related… more
    Qualcomm (12/23/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design ...and propose and implement new ways to improve the efficiency in the GPU/CPU clocking design . What… more
    NVIDIA (10/22/24)
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  • Digital ASIC Micro Architect Design

    Google (Mountain View, CA)
    …computer architecture concepts, including microarchitecture, multimedia architecture, and silicon design . Preferred qualifications: + Master's degree or Phd in ... codecs, display, computer cores and machine learning accelerators). + Experience in ASIC development methodology and require Verilog RTL development as per the… more
    Google (12/10/24)
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  • Senior ASIC Integration and CAD…

    Palo Alto Networks (Santa Clara, CA)
    …You will collaborate closely with the ASIC vendor and the PANW ASIC design team in floorplanning, closing timing, validating constraints, and optimizing ... we all win with precision. **Your Career** As an ASIC Integration and CAD Engineer , you will...RAMs, CAMs, custom IPs, and IO pads throughout the design hierarchy + Collaborate with external ASIC more
    Palo Alto Networks (12/21/24)
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  • ASIC Design Engineer

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... techniques to improve RTL code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and ASIC more
    Google (12/10/24)
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  • ASIC Engineer , Emulation

    Meta (Sunnyvale, CA)
    …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Emulation Responsibilities: 1. Develop emulation testbenches in System ... **Summary:** Meta is hiring ASIC Emulation Engineers within our Infrastructure organization. We...SOC interfaces. 7. Develop emulation validation components for validation efficiency in testing, debug and automation. 8. Develop and… more
    Meta (10/17/24)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... efficiency + You are expected to understand the design and implementation, develop power metrics and drive power...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
    NVIDIA (10/23/24)
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  • Senior ASIC Front End Infrastructure…

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking elite ASIC RTL/Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position ... team of dedicated Infrastructure engineers continuously upgrades the NVIDIA Hardware design environment. We focus relentlessly on Infrastructure improvement so that… more
    NVIDIA (11/07/24)
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  • ASIC Design Verification…

    Broadcom (San Jose, CA)
    …Ethernet solutions that deliver unprecedented performance at critically important power efficiency ._** **_We are looking for highly skilled and efficient Constrained ... Random Design Verification engineers that want to verify new designs...of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products.… more
    Broadcom (11/06/24)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are looking for a Senior Verification Engineer to join our Display Team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... creativity and intelligence! In this role, you will work closely with Architects and ASIC Engineers to define and implement test plan, own all tasks involved in… more
    NVIDIA (10/22/24)
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  • Sr.Staff SoC Lead design verification…

    Qualcomm (Santa Clara, CA)
    …Summary:** As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in ... and emulation strategies) to continuously push the quality and efficiency of test benches + Act as a technical...Science, Engineering, or related field and 6+ years of ASIC design , verification, validation, integration, or related… more
    Qualcomm (10/29/24)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital uArchitecture and ... firmware, and algorithms.We are growing our Graphics & Display ASIC Design and uArchitecture team within RL...experience. 9. 8+ years of experience as a Hardware Design Engineer for production silicon shipped in… more
    Meta (12/20/24)
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  • SoC Design Engineer , Google Cloud

    Google (Sunnyvale, CA)
    …also be involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers. Behind everything our users see ... with SOC implementation standards and interfaces (eg AXI). + Experience as a design lead or technical management of RTL engineers. + Experience with scripting… more
    Google (12/20/24)
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  • SoC UPF Design Engineer , Google…

    Google (Sunnyvale, CA)
    …also be involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers. Behind everything our users see ... emphasis on computer architecture, or a related field. + Experience with low-power design techniques such as clock gating, power gating, and DVFS. + Experience with… more
    Google (12/18/24)
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  • Silicon Digital Design Engineer III

    Google (Mountain View, CA)
    …or Computer Science, with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks, reset checks and low ... power design . + Experience in ASIC ...the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. Google's mission is to organize the… more
    Google (12/07/24)
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