- Cisco (San Jose, CA)
- …execution to ensure progress and accuracy. Who you are You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing ... most complex ASICs being developed. Who you'll work with You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer - STA to continue to innovate on behalf of our customers. We are a part ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs.… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....for RDC. 8. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more
- Amazon (Sunnyvale, CA)
- …front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining ... test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans - Write high quality documents to guide a scalable team Basic Qualifications - Bachelor's degree in Electrical Engineering, Communications Engineering or… more
- Google (Mountain View, CA)
- …in Physical Implementation of High Performance ASICs. + Experience building ASIC implementation flows (RTL-to-GDS2). Preferred qualifications: + Master's degree or ... field. + Experience as technology lead driving Physical Implementation for complex ASIC project(s). + Experience with pre-silicon and post-silicon Design For Test… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing. + Good knowledge of extraction,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL integration, maintain the timing constraint, ... Synthesis, Place and Route, Static timing analysis ( STA ), timing closure, power optimization, and physical verification for both of block and Chip top level You will… more
- NVIDIA (Santa Clara, CA)
- …industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams with advanced implementation ... experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools... methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment,… more
- Google (Sunnyvale, CA)
- …+ Experience in cross-functional collaboration with chip top design, physical design, STA , package, system design, and validation teams. + Experience in programming ... Understanding of on and off chip power delivery and STA /voltage budget. + Familiarity with memory testing, next generation...integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... at circuit level in both spice and transistor level STA . + Understanding crosstalk, noise, OCV, timing margins, Clocking...Stand Out From the Crowd: + Prior experience in ASIC Design and Timing. + Familiarity with ASIC… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... Electrical or Computer Engineering with 5+ years experience in ASIC Design and Timing. + Proven understanding of circuit...at circuit level in both spice and transistor level sta . + Understanding crosstalk, noise, OCV, timing margins. Familiarity… more
- Integense (San Jose, CA)
- Integense Micro is disrupting the semiconductor supply chain with innovative ASIC solutions. As an established provider of integrated circuit solutions for the ... + Experienced in all Front and Back End activities - RTL, Verification, Synthesis, STA , DFT, ATPG, etc. + Adept with System Verilog, C, and various scripting… more
- Siemens Digital Industries Software (Fremont, CA)
- …+ Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... Design/Verification, LEC, STA analysis o Integration and validation of Silicon-on-Chip IP integration and validation o Place and Route solutions: Siemens (Aprisa,… more