- Qualcomm (Santa Clara, CA)
- …future for all. **Responsibilities** Candidate will be responsible for developing next generation power and limits system. With HPC, AI, and automotive system ... the candidate to understand and work on all aspects of power control and limits architecture, micro architecture and interactions with system, SW and product… more
- Qualcomm (Santa Clara, CA)
- …of experience in one or more system architecture technology areas and products (eg, Power System, Shared Resource Management , Limits /Thermal Management , ... at the SoC, sub-system or large IP levels as micro- architect or architect + Ability to apply...shared memory, I/O, coherency, compression, security + Resource and Power Management + Security Architecture + System-level… more
- NVIDIA (Santa Clara, CA)
- …experience in a related hardware engineering role. + Proven experience improving testability limits and aligning product needs with ATE power , thermal, and ... integration in a hardware engineering context. + Familiarity with system-level trends in power , thermal management , and their impact on quality and reliability.… more
- Qualcomm (Santa Clara, CA)
- …of experience in one or more system architecture technology areas and products (eg, Power System, Shared Resource Management , Limits /Thermal Management , ... Group > SoC Architecture **General Summary:** As a SoC Performance Architect , you will create performance and power models for the fabric NoC / DRAM controller /… more
- Qualcomm (Santa Clara, CA)
- …of experience in one or more system architecture technology areas and products (eg, Power System, Shared Resource Management , Limits /Thermal Management , ... to a variety of opportunities and choices. We are seeking a Memory System Architect with experience and expertise in SRAM, DRAM, DDR, LPDDR, HBM, GDDR and newly… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …solutions. Do you want to make a difference and be challenged? Design Engineering Architect in physical design, SSG. * This technical and project leadership role is ... with leading foundries such as TSMC, Samsung, Intel to achieve best Performance/ Power /Area (PPA) for Cadence IPs, and guiding Cadence worldwide physical design teams… more
- Qualcomm (Santa Clara, CA)
- …of experience in one or more system architecture technology areas and products (eg, Power System, Shared Resource Management , Limits /Thermal Management , ... SMMU, Caches) HW architecture + Strong knowledge in Quality of Service, Clocks, Power management , Security and Debug architectures and their respective software… more