- Cisco (San Jose, CA)
- …execution to ensure progress and accuracy. Who you are You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing ... and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and … more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer - STA to continue to innovate on behalf of our customers. We are a part ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. -… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $138,600 to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to enable new and differentiating technologies.. + In this role, the Solutions Engineer (SE) is expected to work both independently and in collaboration with other ... team members to address customer issues and to identify new opportunities or Risk that are linked to those activities + The SE will interact with Product Engineering/RnD Team as well as Key Technologists at customer site to develop and enable new… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...which is the primary task. + Develop flows/recommendations on STA and PNR in deep submicron physical effects aging,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …maintain the timing constraint, Synthesis, Place and Route, Static timing analysis ( STA ), timing closure, power optimization, and physical verification for both of ... responsible for interfacing with the Physical Design team on STA , timing closure and P&R, and participating in silicon...timing closure flow and methodology. Strong command of synthesis, STA , design for test, and design methodologies Ability to… more
- Meta (Sunnyvale, CA)
- …stack, from transistor, through architecture, to firmware, and algorithms. As a DFT Engineer at Meta Reality Labs, you will play an integral role in implementing ... products to millions of customers quickly. **Required Skills:** DFT Engineer Responsibilities: 1. Work with the Silicon teams to...on industry standard tools 4. Work with designers on STA , physical, power and logical issues related to DFT… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using advanced optimization ... reset sequence for RDC. 8. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze the inter-block… more
- Google (Sunnyvale, CA)
- …+ Experience in cross-functional collaboration with chip top design, physical design, STA , package, system design, and validation teams. + Experience in programming ... Understanding of on and off chip power delivery and STA /voltage budget. + Familiarity with memory testing, next generation...integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world! We are currently looking for a SRAM Timing Engineer to join our team of dedicated engineers developing custom SRAM circuits that help ... identify improvements and solutions and deploy newer features. + Lead implementation of STA solutions for multiple circuit design and technology teams and 3rd party… more
- Google (Mountain View, CA)
- …Test (DFT). + Experience in sign-off convergence including Static timing analysis ( STA ), electrical checks, and physical verification. + Experience in package design ... (CTS), Design For Test (DFT) (Scan, MBIST, BISR), Static Timing Analysis ( STA ), signal/power integrity (SI/PI), Layout Versus Schematic and Design Rule Checking… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …level simulations to verify functionality. + Perform and help debug Synthesis/ STA scripts/constraints. + Participate in development of Application notes, Training ... + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end experience is a plus + Familiarity with industry standard DFT… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of ... to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- Meta (Sunnyvale, CA)
- …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more
- NVIDIA (Santa Clara, CA)
- …to join us today. We are now looking for a highly motivated DFT Engineer to join this dynamic and innovative hardware team at NVIDIA. Our Design-for-Test Engineering ... vendor tools + Good exposure to multiple domains including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs +… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... how to verify them at circuit level in both spice and transistor level STA . + Understanding crosstalk, noise, OCV, timing margins, Clocking specs (jitter, IR drop,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior DFT Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the ... and IOs + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + Strong… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + Strong ... our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! The base… more