- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 -… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- ManpowerGroup (New Almaden, CA)
- ** Senior ASIC Design Engineer** Our client in **San Jose, CA** is looking for hardworking, motivated talent to join their team. Don't wait apply today! ... Holiday Pay, Referral program bonus, etc. **Job Description** + Focus on analog/mixed-signal ASIC design in advanced nodes. + Manage PDK libraries and drive… more
- NVIDIA (Santa Clara, CA)
- …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the… more
- NVIDIA (Santa Clara, CA)
- …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...SOC clocking. The team collaborates with the front end design team to understand the clocking requirements for the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 8 years of experience with ASIC design flow in advanced nodes (including synthesis, PNR, STA, and formal ... LP, or Incisive/VCS. Preferred qualifications: + Experience in low power digital ASIC design including UPF/CPF, multi-voltage domains, and on-chip power… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...expertise is required as is a deep understanding of ASIC design flow including RTL design… more
- Renesas (San Jose, CA)
- …ECOs on RTL, synthesized, and post route netlists + Fluent in Verilog RTL coding and ASIC design methodology is a must + Competence in developing design ... Senior Staff Engineer, Electrical Design Job...support is a plus + Experience in DFT or physical design is a plus + Experience...communications skills + 8+ years of direct experience in ASIC /IC design with deep knowledge of whole… more
- NVIDIA (Santa Clara, CA)
- …the opportunity to build complex GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design , CAD, Package Design , Software, DFT and ... NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design...design quality checks and reviews to present the physical design team with high-quality RTL What… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …The Position Requirements are + Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4 years of experience. Master's ... degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is...Static Timing Analysis is required + Prior experience with ASIC digital implementation flows and EDA tools is required,… more
- NVIDIA (Santa Clara, CA)
- … Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic ... high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog… more
- NVIDIA (Santa Clara, CA)
- … Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing ... team of Photonics, CMOS, Electronics, and Systems engineers + Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits,… more
- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... What you'll be doing: + Lead and implement IC physical layout for mixed-signal functions like high speed SerDes,...and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using Cadence tools.… more
- Amazon (Sunnyvale, CA)
- …phases of Silicon development which are architecture definition, RTL design , Verification, IP design , Physical design , post silicon design and bring ... will interface with cross-functional engineering and program/product management teams to develop ASIC /SOC solutions that will go into Amazon Devices. In this role… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies...etc. + Prior internships or experience in experience in ASIC Design and Timing. With competitive salaries… more
- NVIDIA (Santa Clara, CA)
- …Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, Product teams and Physical Design teams to ... We are looking for a Senior Emulation Power Engineer! NVIDIA prides in having...power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power… more
- NVIDIA (Santa Clara, CA)
- …and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams ... We are now looking for a Senior Power Optimization and Analysis Engineer! NVIDIA prides...power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power… more
- NVIDIA (Santa Clara, CA)
- …with 3+ years of CAD experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools + Software engineering ... implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design...Tcl, C/C++ + Knowledge or experience with logic synthesis, physical design , formal equivalence checking. + Proven… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In this… more