- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Product Development Engineer to join our outstanding Automotive/Embedded Systems team! As part of an Operations Engineering team ... Experience with ASIC mixed-signal design, characterization and qualification + Knowledgeable in DFT and device physics + Proficient in statistical modeling of data… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to ... need to see: + BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD) a plus. + 5+ years… more
- NVIDIA (Santa Clara, CA)
- …these meaningful changes in automotive industry, We are now looking for a Senior Reliability Engineer . The position is an individual contributor role, working ... engineering team to develop reliability qualification plan. + Work closely with DFT team and product engineering team for qualification test program, validation and… more
- Power Integrations (San Jose, CA)
- Senior Test Engineer Location: San Jose,...with IC design team to understand design specifications and DFT proposals. + Create test programs in C language, ... debug and validate silicon on ATE + Design test interface hardware for ATE + Innovate to improve robustness of test solution and improve cost of test. + Supports and is responsible for sustaining and continuous improvement of production tests for multiple… more
- NVIDIA (Santa Clara, CA)
- We are looking to hire a Senior Board Test Engineer who will work in the Test Solutions Group at NVIDIA developing manufacturing GPU/CPU test solutions for Data ... automated Diag generation and validation infrastructure. + Review and provide feedback for DFT in the early design stages. + Debug complex hardware and software… more
- NVIDIA (Santa Clara, CA)
- …deliver extraordinary solutions in a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to ... Excellent problem solving, collaborative, and interpersonal skills. + Knowledgeable in DFT architecture, BIST, fault models and fault detection methods, HTOL… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Logic Design Engineer ! Asa member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and ... of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT , timing analysis, floor-planning, ECO, bring-up & lab debug. + Strong… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is ... experience in implementing Test plans for pre-silicon platforms. + Understanding of DFT /IST is optional. We have some of the most forward-thinking and hardworking… more
- NVIDIA (Santa Clara, CA)
- Are you looking for an SOC Design Engineer opportunity? If yes, come and join us. The complexity of the chip has greatly increased over the years. We are now packing ... System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL...with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing: +… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to ... flow. + Strong hands-on debugging capability and problem-solving skills. + Background in DFT timing closure for various modes eg scan shift and capture, transition… more
- Palo Alto Networks (Santa Clara, CA)
- …all win with precision. **Your Career** As an ASIC Integration and CAD Engineer , you will ensure that the ASICs in our groundbreaking next-generation firewall ... subsystem and top levels, ensuring robust solutions for clocks, resets, feedthroughs, and DFT + Integrate RAMs, CAMs, custom IPs, and IO pads throughout the design… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... + Understanding of high-speed clock distribution and planning as well as impact of DFT logic in timing convergence. + Knowledge of circuits and SPICE, as well as… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the design of ... of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT , timing analysis, floor-planning, ECO, bring-up & lab debug. + Strong… more
- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of SOC ... other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.… more
- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and ... members, we deliver clock information to GPU, CPU and SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.… more
- NVIDIA (Santa Clara, CA)
- …us today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to ... significantly. Modern clocking design needs to balance high frequency clocks with power, DFT , noise, circuit and physical design constraints. What you'll be doing: +… more
- NVIDIA (Santa Clara, CA)
- …Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with compute farm interaction: software deployment, performance ... optimization, containers, etc. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're… more
- NVIDIA (Santa Clara, CA)
- …circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design-for-test ( DFT ) and logic design is a plus. + Proficiency in scripting language, ... such as, Perl, Tcl, Make and automation methods/algorithms a certain plus. + Prior leadership experience a certain plus. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable… more