- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role ... in improving the netlist and timing quality of our designs and if you are...teams. + Work on project execution as well as methodology improvements. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. + Finding the right tradeoffs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing closure work for DFT logic in our GPUs, CPUs, and SOCs at block ... full chip level + Work on all aspects of timing for DFT such as timing constraints,...to seamlessly move projects forward with new features and methodology improvements What we need to see: + Bachelor's… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across ... + Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Familiar with various process related design… more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We ... patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through...for high coverage on silicon - Review sign-off level timing closure using static timing analysis of… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + ... reviews + Cover digital backend design from synthesis, static timing and logic equivalent checking + Creating documentation targeting...+ Fluent in Verilog RTL coding and ASIC design methodology is a must + Competence in developing design… more
- J&J Family of Companies (Santa Clara, CA)
- Senior FPGA Engineer - 2406199055W **Description** Ethicon, part of Johnson & Johnson Medical Devices Companies, is recruiting for a ** Senior FPGA Design ... life-changing impact. For more information, visit www.ethicon.com (https://protect-us.mimecast.com/s/JaDLCkRg2ki5NlORTVNkS-?domain=ethicon.com) The Senior Field Programmable Gate Array (FPGA) Design Engineer… more
- BAE Systems (San Jose, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Senior Principal Front End ASIC Design Engineer (Hybrid)** **102613BR** EEO ... of a large company. We are looking for a senior level chip designer who has strong proficiency in...both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout phase + Verification- executing testbench… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal Integrity Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI model correlations using lab measurements to improve modelling tool/ methodology . + Package substrate and board layout SI design...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital ... in one or more of the following areas: Synthesis, Place and Route, timing and power signoff. + Understanding and proliferating Cadence flow solutions in the… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation SoC solutions. We are looking for special individuals with passion and ... with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- Amazon (Sunnyvale, CA)
- …and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of the… more
- Qualcomm (Santa Clara, CA)
- …team to plan/track project execution from Synthesis through GDSII including domain signoffs ( Timing , PDN, PDV) * Lead the creation and maintenance of credible and ... and solve problems to solutions. * Roll-up and report regularly to senior management-executives on key development milestones, budget, metrics, risks, and mitigation… more