- Google (Sunnyvale, CA)
- SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more ... and its integration within AI/ML-driven systems. As a System on a Chip ( SoC ) Physical Design Engineer , you will collaborate with Register-Transfer Level… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds to build ... power everything from AI to gaming! As a Senior SOC Design Engineer , you'll work...integrating advanced ASICs, and partnering with experts in ASIC design , Physical design , CAD, Package… more
- SpaceX (Sunnyvale, CA)
- ASIC/ SOC DFT Engineer (Silicon Engineering) Sunnyvale,...design readiness for scan insertion through RTL and physical design Scan Design Rule ... the ultimate goal of enabling human life on Mars. ASIC/ SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...content through gate level simulation + Collaborate with circuit physical design team, ATPG team and manufacturing… more
- Capgemini (Santa Clara, CA)
- **About the Role** Join our Center of Excellence as a ** SOC Solution Engineer ** , where you will **architect, design , and deliver innovative System-on-Chip ( ... teams to resolve issues and accelerate delivery. **Your Profile** + **15 years** in SoC design /verification with expertise in UVM, UPF, and protocol VIPs. +… more
- SpaceX (Sunnyvale, CA)
- ASIC/ SOC DV Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... the ultimate goal of enabling human life on Mars. ASIC/ SOC DV ENGINEER (SILICON ENGINEERING) At SpaceX...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per… more
- SpaceX (Sunnyvale, CA)
- …work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your ... Sr. SOC /ASIC DFT Engineer (Silicon Engineering) Sunnyvale,...fast, reliable internet to millions of users worldwide. We design , build, test, and operate all parts of the… more
- SpaceX (Sunnyvale, CA)
- Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...and capabilities of the Starlink network. RESPONSIBILITIES: + Perform SOC top level physical design ;… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... for next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a...collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs… more
- Meta (Sunnyvale, CA)
- …on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power… more
- MetaOption, LLC (Milpitas, CA)
- …Design Engineer - Milpitas, CA We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs ... with 5+ years experience; MSEE preferred + Strong experience in ASIC physical design and SoC development (28nm/16nm) + Proficient in ICC2/Innovus, scripting… more
- Microsoft Corporation (Mountain View, CA)
- …Python OR equivalent experience. - 10+ years of relevant experience. - Expertise in CPU/ SoC design principles. - For Front-End Handoff CAD Roles: - In-depth ... Emulation, Design Synthesis, RTL Power Anaysis, PD Handoff and SoC integration. This team supports numerous simultaneous projects within Microsoft by developing… more
- Microsoft Corporation (Mountain View, CA)
- …passionate engineers to help achieve that mission. We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on ... program you will be interacting with various teams, including architecture, verification, and physical design , ensuring that the design is implemented and… more
- Microsoft Corporation (Mountain View, CA)
- …engineers to help achieve that mission. We are looking for a **Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... program you will be interacting with various teams, including architecture, verification, and physical design , ensuring that the design is implemented and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a group of ... of our Memory Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team to deliver a… more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible...will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage… more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... The clocks group is looking for an outstanding ASIC engineer to join the team. The Team is responsible...will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage… more
- Broadcom (San Jose, CA)
- …+ Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must. **Additional Requirements:** + Good problem solver. + Self ... and/or timing (constraints, STA) can be considered for this position. + Proficient in design implementation activities both at block and SoC level. + Well… more
- Broadcom (San Jose, CA)
- …dynamic environment. + Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must. + Should have worked on tape out of at ... timing (constraints, STA) can be considered for this position. + Extremely proficient in design implementation activities both at block and SoC level. + Well… more