- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals ... What you will be doing: + Responsible for developing and optimizing semi- custom design methodologies, work with internal and external collaborators and IP Vendors… more
- NVIDIA (Santa Clara, CA)
- …power NVIDIA's next generation of AI chips. What you will be doing: + Drive robust methodology for timing analysis of custom circuit IP. + Support SRAM and ... the world! We are currently looking for a SRAM Timing Engineer to join our team of...other custom circuit design engineers through successful timing convergence towards tape-out. + Work closely with design… more
- Google (Sunnyvale, CA)
- …Computer Science, or equivalent practical experience. + 5 years of experience in static timing (ie, to create full chip timing constraints, perform full chip ... static timing analysis and timing ECO creation). + Experience in working across various...or more aspects of physical design or physical design flow/ methodology , to successful tape-outs and shipping silicon. + Experience… more
- Qualcomm (Santa Clara, CA)
- …envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the world's best implementation tools and ... flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. **Minimum Qualifications:** * Bachelor's degree in… more
- Amazon (Sunnyvale, CA)
- …an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of ... the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design… more
- Google (Sunnyvale, CA)
- …budget. + Familiarity with memory testing, next generation memory, chiplet standards and timing budget methodology . Be part of a diverse team that pushes ... boundaries, developing custom silicon solutions that power the future of Google's...integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package… more
- NVIDIA (Santa Clara, CA)
- …with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation...be. What you'll be doing: + Work in NVIDIA's semi- custom engineering team building customized chip solutions targeting data… more
- Qualcomm (Santa Clara, CA)
- …will be responsible for providing technical program management support to our Custom CPU Engineering team including the following responsibilities: * Work with ... project execution from Synthesis through GDSII including domain signoffs ( Timing , PDN, PDV) * Lead the creation and maintenance...or PhD degree in Engineering * Experience as an engineer in chip development and integration into hardware or… more