• ASIC DFT Verification

    Cisco (San Jose, CA)
    …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... chip tape out, including test coverage, STA. * Prior experience with pre-silicon DFT implementation and verification flows, and post-silicon test bring up… more
    Cisco (10/19/24)
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  • ASIC Engineer, DFT

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT Responsibilities: 1. Develop and implement DFT strategies… more
    Meta (10/18/24)
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  • ASIC DFT Implementation Lead

    Cisco (San Jose, CA)
    …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... custom DFT logic & IP integration; familiarity with functional verification * DFT CAD development & EDA interactions - Test Architecture, Methodology and… more
    Cisco (11/01/24)
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  • DFT Design Engineering Architect - AE

    Cadence Design Systems, Inc. (San Jose, CA)
    …want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design For Test ( DFT ) Architect. An intimate knowledge and experience in ... highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. + Prior15+ years of professional… more
    Cadence Design Systems, Inc. (11/28/24)
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  • ASIC Design for Test Technical

    Cisco (San Jose, CA)
    …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... DFT logic & IP integration; familiarity with functional verification * DFT CAD development - Test Architecture, Methodology and Infrastructure * Background… more
    Cisco (11/15/24)
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  • ASIC Design Technical Leader…

    Cisco (San Jose, CA)
    …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
    Cisco (12/12/24)
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  • ASIC STA Engineering Technical

    Cisco (San Jose, CA)
    …of the most complex ASICs being developed in the industry. Your Impact As an ASIC Engineering Technical Leader, you will be responsible for leading the design, ... verification , and software, to ensure alignment and resolve technical challenges. Responsibilities will include: * Leading architecture design and optimization… more
    Cisco (12/04/24)
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  • ASIC Technical Lead

    Cisco (San Jose, CA)
    …junior engineers on performing project tasks and problem solving. * Collaborate with the verification , PD, DFT , Package and SW teams to develop next generation ... AI Switching ASIC . * Perform diagnostic and post silicon validation tests...delivering project milestones and deadlines. * Ability to communicate technical concepts to audiences spanning executives to junior engineers… more
    Cisco (12/18/24)
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  • ASIC Engineer II (Full Time) United States

    Cisco (San Jose, CA)
    …processor architecture, Ethernet processing, digital signal processing, high-speed logic design & verification , memory designs, and physical design & DFT . Why ... you directly if a relevant position opens. Who You'll Work With The ASIC Group works closely with other development teams within Cisco, including marketing, system… more
    Cisco (11/18/24)
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  • Silicon Digital Design Verification

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 5 years of experience leading digital verification using SystemVerilog for ASIC designs. + Experience developing and ... and deliverables. + Work closely with system, software, design, Design for testing ( DFT ) and physical implementation stakeholders to make technical decisions. +… more
    Google (12/10/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    …Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...Science, with 7+ year minimum of hands-on experience in ASIC implementation and Physical verification * Prior… more
    Cisco (10/23/24)
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  • COPD (Customer Owned Physical Design) Engineer

    Broadcom (San Jose, CA)
    …in physical design and STA 5. Well verse in EDA tools for physical design verification and sign-off. 6. Knowledge of ASIC design flow including physical design, ... design, chip architecture, microarchitecture, Verilog RTL coding 3. Front-end logic design verification , DRC, logic synthesis 4. Knowledge of DFT methods… more
    Broadcom (11/28/24)
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  • Silicon Test Engineer, SoC, Platforms

    Google (Sunnyvale, CA)
    …in test engineering or product engineering. + Experience in Application-Specific Integrated Circuit ( ASIC ) or SoC DFT test development, bring-up, or debug for ... + Master's degree in Computer Science, Electrical Engineering, or in a related technical field. + 10 years of experience in test engineering or product engineering.… more
    Google (12/21/24)
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  • SoC UPF Design Engineer, Google Cloud

    Google (Sunnyvale, CA)
    …intent specification, verification , and implementation. + Experience with formal verification methods and design for testability ( DFT ) techniques. + ... design and implementation of global communication busses, and integration of complex ASIC designs. This is a cross-functional and central role that will require… more
    Google (12/18/24)
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  • Physical Design Lead, Static Timing Analysis

    Google (Sunnyvale, CA)
    …degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. + 10 years of experience ... static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing… more
    Google (12/21/24)
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  • Manager II, Silicon Digital Design

    Google (Mountain View, CA)
    …in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset. + Knowledge of ASIC Verification , DFT , synthesis, STA, or Physical Design. ... or Computer Science, with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks, reset checks and low power… more
    Google (12/07/24)
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  • Hardware (CPU, GPU, SoC, Digital Design, DV)…

    Qualcomm (Santa Clara, CA)
    …(micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design-for-Test ( DFT ), Physical Design (Place & route, CTS, timing closure), ... Pre-silicon Verification (DV), Emulation, Post-silicon Validation (VI), CAD, GPU Design,...professional experience in one or more of the following technical tracks: **_GPU_** + Engineering design and development in… more
    Qualcomm (11/19/24)
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  • Digital Design Engineer

    Broadcom (San Jose, CA)
    …Candidate Account, please Sign-In before you apply.** **Job Description:** Broadcom ASIC product division is a leader in semiconductor innovation, delivering ... micro-architecture, and design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness,… more
    Broadcom (12/18/24)
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  • Senior GPU Hardware Security Architect, Memory…

    NVIDIA (Santa Clara, CA)
    …+ A working understanding of floor-planning, ASIC physical design, VLSI and DFT . + A hands on technical background; excellent C programming and low-level ... details for features that improve security of our GPUs. + Drive implementation and verification of hardware features that improve security of our GPUs. + You will… more
    NVIDIA (11/13/24)
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