- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Mechanical/Thermal modeling focus for its ASIC packaging team to support the ... they can create as part of a world-class engineering team. **Required Skills:** ASIC Packaging Engineer Responsibilities: 1. As an ASIC Packaging… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... chip development. + Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities +… more
- Google (Mountain View, CA)
- ASIC Lead Engineer , Project Taara (Fixed Term) Hardware Engineering Mountain View, CA This is a fixed-term contract position for 12 months About the team: At X ... About the Role: The Taara Project is seeking an ASIC lead engineer to drive the next...+ Familiarity with IC integration with photonics and related packaging technology. Ability to evaluate the impact of different… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....24. Experience in the 3D-IC technology, methodology, and advanced packaging . 25. Experience in validating Power Distribution Network (PDN),… more
- Google (Mountain View, CA)
- Senior Mixed-Signal ASIC Designer, Project Taara Hardware Engineering Mountain View, CA This is a fixed-term contract position for 12 months About the Team: Project ... Taara About the role: The Taara Project is seeking a Senior Integrated Circuit engineer leading the next generation circuit design as part of the R&D team developing… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced Silicon Packaging design Engineer for its Ecosystem and Technical Operation team to support the development of ... custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC...part of a world-class engineering team. **Required Skills:** Silicon Packaging Design Engineer Responsibilities: 1. Perform package… more
- Cisco (San Jose, CA)
- …integration. We are focused on all the latest technologies including optical and advanced packaging . What You'll Do Cisco SiliconOne ASIC team is looking for an ... internal platforms and external customers. We are a specialized ASIC team with experts in all aspects of Silicon...of teammates. Who You Are You are a mechanical engineer with substrate expertise working on cutting-edge technologies and… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **R&D Staff Engineer ** The ideal candidate will have expertise in integrated-circuit process ... **Key Qualifications** + Broad knowledge of advanced silicon and packaging process technologies + Working knowledge of the Advanced...**Job Description** + Provide design support for IP & ASIC to create robust designs in line with advanced… more
- Google (Sunnyvale, CA)
- …related field, or equivalent practical experience. + 10 years of experience in ASIC physical design flows and methodologies in advanced process nodes. + Experience ... . + Own interposer routing necessary for 2.5D or 3D packaging (ie, custom signal routing, shielding and power/ground distribution). + Connect… more
- Broadcom (San Jose, CA)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** The ASIC Products Division at Broadcom has developed some of the most complex IC ... 3D and 2.5D interconnects. We are seeking a design engineer with physical layout skills to develop our next...new ideas, design the next generation of leading edge ASIC products, and work on the most advanced technologies… more
- Actalent (San Jose, CA)
- Job Title: Mechanical Engineer Job Description Seeking an experienced package mechanical FEA engineer for very-large and complex packages for industry-leading ... Responsibilities + Perform finite element analysis (FEA) for complex ASIC packages. + Use ANSYS to model and correlate...+ Analyze stress and material properties. + Conduct IC packaging , including flip chip, BGA, and MCM. + Devise… more
- SpaceX (Sunnyvale, CA)
- …includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations + Accurately estimate the schedule ... IC Layout Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking an experienced Signal Integrity Engineer to join our Platform HW Interconnect team, focusing on Power Integrity and Signal Integrity for ... our MTIA (Meta Training Inference ASIC ) reference module and next-generation System on Wafer (SOW)...Wafer (SOW) reference module design. **Required Skills:** Signal Integrity Engineer Responsibilities: 1. Work with vendors to select and… more
- Micross Components (Milpitas, CA)
- …range from bare die and wafer processing to advanced and custom packaging to component modifications and related interconnect offerings. With ambitious private ... a key role in these evolutions. Summary: The Semiconductor Reliability Test Engineer will provide technical support to STS' Environmental Screening area which… more
- Google (Sunnyvale, CA)
- …performance, efficiency, and integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package design with signal/power ... the part of a larger team with Chip Architects, ASIC Engineers, Physical Design and other SI/PI Engineers. You...Design, software team and vendors. You will drive chip packaging signal and power implementations from product planning to… more
- Cisco (San Jose, CA)
- …methodology from conception to production. * You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications ... collaborate in order to provide an optimized design that will integrate into the ASIC . In addition, you will have the opportunity to interact with other Acacia… more