- Actalent (West Menlo Park, CA)
- Silicon Digital Design / ASIC Engineer III (Fully...in future AR products. The successful candidate will own ASIC IP RTL implementation for IP blocks, ... testing, and support integration into larger SOC environments. Position: Silicon Digital Design Engineer Location: Remote Pay rate: $70-90/hour Duration: 12… more
- BAE Systems (San Jose, CA)
- …be available based on position level and/or job specifics. **Senior Principal Front End ASIC Design Engineer (Hybrid)** **102613BR** EEO Career Site Equal ... designer who has strong proficiency in both + ASIC design - performing architecture design , RTL coding/simulation, timing closure at layout phase +… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... Integration. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power...Computer Science, or a related field. + Experience with ASIC design methodologies for clock domain checks,… more
- Meta (Sunnyvale, CA)
- …Area. 14. Knowledge of front-end and back-end ASIC tools. 15. Experience with RTL design using SystemVerilog or other HDL. 16. Experience managing multiple ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... & bus protocols, interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis… more
- SpaceX (Sunnyvale, CA)
- Principal SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... ultimate goal of enabling human life on Mars. PRINCIPAL SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL / design … more
- SpaceX (Sunnyvale, CA)
- …impact on synthesis, physical design and timing closure + Deep understanding of ASIC design flow, top-down and bottom-up design methodologies + Knowledge ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In… more
- NVIDIA (Santa Clara, CA)
- …+ 5 years of proven experience with tools and methodologies for ASIC design and verification. + Direct experience with RTL Linting EDA tools. + Proficiency ... world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation...to provide methodology insights. + Act as liaison between ASIC designers and EDA vendors. What we need to… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Design Verification Engineer Responsibilities:...scratch. 10. Experience debugging fails to the line of RTL , closing out bug fixes, using Verdi or equivalent… more
- Meta (Sunnyvale, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Cisco (San Jose, CA)
- …the lab. Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... or Master's degree in Electrical or Computer engineering. * 8+ years of ASIC Design experience. * Excellent Verilog/System Verilog programming skills. *… more
- NVIDIA (Santa Clara, CA)
- …flow experience + Hold a basic sense of verification methodology + Good understanding of ASIC design flow including RTL design , verification, logic ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design ...modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design , synthesis, timing + Silicon bring-up… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to ...Systems design . + A deep understanding of ASIC design flow including RTL ... be doing: + As a key member of our design team, you will be responsible for the micro-architecture...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- Amazon (Sunnyvale, CA)
- Description As a ASIC Design Engineer , you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop ... IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional...from architecture guideline and model analysis. - Experience in RTL coding and debug, as well as performance/power/area analysis… more
- Meta (Menlo Park, CA)
- …data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development 2. RTL development using ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...one of these skills (minimum 3 years): Micro-architecture and RTL development for complex control and data path IPs,… more
- NVIDIA (Santa Clara, CA)
- …performance semiconductor designs. + Verilog expertise required as is a deep understanding of ASIC design flow including RTL design , verification, logic ... We are now looking for a Logic Design Engineer . As a member of...tasks include: writing readable high performance and low power RTL , Synthesis and Timing closure, and design … more
- Meta (Sunnyvale, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to ... the opportunity to be responsible for the micro-architecture and design including RTL design , synthesis,...+ You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT,… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design ...thrive in a dynamically changing environment. + Experience in RTL design (Verilog), verification and logic synthesis.… more
- Google (Sunnyvale, CA)
- …(ASICs). + Familiarity with ASIC standard interfaces and memory system architecture. As a ASIC Design Verification Engineer , you will be part of a team ... a related field. + 6 years of experience in design verification. + Experience with one or more of...dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in… more