• Integration Methodology

    Google (Mountain View, CA)
    …on low power design. + Experience with new process technology based SoC integration flow development and tape-out. + Experience with scripting languages (ie, ... at Google (https://careers.google.com/benefits/) . + Develop, support and execute SoC integration flow development and execution, including Multiple scenarios of… more
    Google (06/20/24)
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  • Physical Design Flow

    Google (Sunnyvale, CA)
    …QOR metrics, and analyzing trends. + Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC integration and signoff, IP ... tool workflows in semiconductor environments. + Experience developing and supporting ASIC physical design flows and methodologies in process nodes. + Experience with… more
    Google (05/29/24)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …team with varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + Key ... and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips....are needed for NVIDIA chips. + Participate in developing flow and tool methodologies for chip floorplan, power and… more
    NVIDIA (05/09/24)
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  • ASIC Design Verification Engineer (Santa Clara,…

    Qualcomm (Santa Clara, CA)
    …and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology . Involve in developing automation to improve ... power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development… more
    Qualcomm (06/12/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early ... help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical more
    Cisco (06/28/24)
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  • Chief Medical Officer and Senior Associate Dean…

    Lucile Packard Children's Hospital Stanford (Palo Alto, CA)
    …of equity. + Demonstrate financial acumen and a deep understanding of payment methodology , funds flow , physician incentives, and cost control techniques. + ... a key role in strategic planning, program development, and clinical program integration focused on growth and sustainability of the SMCH Enterprise. Represents the… more
    Lucile Packard Children's Hospital Stanford (06/28/24)
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  • Sr. Synthesis & Front-End STA Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …+ Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) + Analysis of clock domain crossing paths at block and ... full chip level + Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration , timing, logical equivalence checking and analysis of various IPs into RTL +… more
    SpaceX (05/09/24)
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  • Sr. Staff Post Silicon CAD Engineer

    Qualcomm (Santa Clara, CA)
    …scripting skills + Strong Unix, Shell, Make skills + Knowledge of ASIC design flow & automation, testbench integration + Knowledge of low level HW/SW interaction ... Engineering **General Summary:** As a CAD Engineer focusing on the post silicon methodology and support, you will work with RTL, architecture, design, DV, software,… more
    Qualcomm (05/25/24)
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  • Sr. Business System Analyst (Salesforce)

    Automation Anywhere, Inc. (San Jose, CA)
    …and best practices through ongoing learning and development. + Maintaining all necessary integration documentation and process flow diagrams. **You will be a ... for Salesforce solutions. + Analyzing business requirements/processes and system integration considerations to determine appropriate technology solutions. + Identifying… more
    Automation Anywhere, Inc. (06/15/24)
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  • SOC Design Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    …+ Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/ integration flow , and design automation. + Strong coding skills ... Engineer with a curiosity about SOC design automation, RTL integration , chip build and assembly, and padring design and...and Tegra chips and interface, directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other… more
    NVIDIA (06/28/24)
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  • Senior Payroll Compliance Analyst - Controller's…

    Lucile Packard Children's Hospital Stanford (Menlo Park, CA)
    …Business Systems Specialist. + . Responsible for designing custom applications, interfaces, Flow charts, scripts, and its impact on applications. + . Audits Kronos ... Manager self-service and approval rules, workflows, Device manager, Attendance Module and Integration , Calendar setup. + . Configures, generates ad hoc Reports and… more
    Lucile Packard Children's Hospital Stanford (06/08/24)
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  • Sr. SOC Design Engineer - STA, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …history. Roles & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA, ... generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf...flow . - Work for Systems and Architecture, SoC Integration , Verification, DFT, Mixed Signal, IP owners, Synthesis, Place… more
    Amazon (05/28/24)
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  • Staff Electrical Engineer/FPGA (Hybrid/Milpitas,…

    BD (Becton, Dickinson and Company) (Milpitas, CA)
    …support packages and bootloaders. . Develop, maintain, and extend automated build flow methodology . Develop and integrate SoC systems, specifically utilizing ... Xilinx or Altera/Intel FPGA technologies. . Support system-level integration of FPGA solutions. . Optimize existing systems for performance improvements and… more
    BD (Becton, Dickinson and Company) (06/06/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early ... help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical more
    Cisco (06/28/24)
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  • Workforce Insights and Analytics Senior Analyst

    SLAC National Accelerator Laboratory (Menlo Park, CA)
    …Determine issues/challenges having the most value to the organization and determine methodology to utilize in interpreting and gathering data from multiple sources ... analytics across the organization. Collaborate with IT to ensure data integration , accessibility, performance of BI tools, and the design and implementation… more
    SLAC National Accelerator Laboratory (06/22/24)
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