- Cadence Design Systems, Inc. (San Jose, CA)
- …flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions . Individual should be able to efficiently work with Cadence R&D to ... constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable… more
- Cisco (San Jose, CA)
- …switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs ... ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR,...this team, you'll be working closely with the timing lead on backend timing signoff, including CDC checks, static… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Technical Skills/ background:** The Design Architect/ Lead will lead a small team of engineers to interact ... timing tool - Ability to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC networks and how they affect the… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Broadcom (San Jose, CA)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...supplies a broad range of semiconductor and infrastructure software solutions . For more information please visit our video library… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design ... place and route, clock methodology, power planning and analysis, timing closure, STA , signal integrity and physical design checks. + Participate in large complex… more
- Qualcomm (Santa Clara, CA)
- …our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. ... Our focus is on developing server-class high performance CPU solutions that are highly optimized for the needs of...the server product. As a CPU Floorplan and Integration Engineer , you will work with microarchitecture, RTL design and… more
- Cisco (San Jose, CA)
- …switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs ... Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus...and reviews for chip tape out, including test coverage, STA . * Prior experience with pre-silicon DFT implementation and… more
- Broadcom (San Jose, CA)
- …division is a leader in semiconductor innovation, delivering cutting-edge custom silicon solutions for AI, networking, HPC among many other applications. We are ... domains crossings. **Key Responsibilities:** **Technical Leadership and Domain Expertise:** + Lead the design and implementation of advanced digital blocks and… more