- Google (Sunnyvale, CA)
- …sign-off for ASICs. Preferred qualifications: + 12 years of experience in the domain of physical design and static timing analysis. + Experience leading one ... timing ECO creation). + Experience in working across various physical design areas (ie, EDA scripting, block...that power all of Google's services. As a Hardware Engineer , you design and build the systems… more
- SpaceX (Sunnyvale, CA)
- Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... goal of enabling human life on Mars. PRINCIPAL SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical… more
- Google (Sunnyvale, CA)
- …tool workflows in semiconductor environments. + Experience developing and supporting ASIC physical design flows and methodologies in process nodes. + Experience ... trends. + Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC...that power all of Google's services. As a Hardware Engineer , you design and build the systems… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... analysis on the design . + Drive the design and physical implementation of digital and/or...Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for… more
- Siemens Digital Industries Software (Fremont, CA)
- …**Req ID:** 396095 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to ... the increasingly complex world of chip, board, and system design . The Calibre(R) team is seeking a highly motivated...The Calibre(R) team is seeking a highly motivated Product Engineer (PE) to help define, promote, and deploy our… more
- NVIDIA (Santa Clara, CA)
- …algorithms, computer architecture and computer science theory + Experienced with VLSI physical design and packaging + Flexibility/adaptability for working in a ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
- Cadence Design Systems, Inc. (San Jose, CA)
- … static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly… more
- NVIDIA (Santa Clara, CA)
- …circuits for hardware security, adaptive clocking and power management solutions + Drive the design and physical implementation of custom digital IPs from RTL to ... impact on the world! What you'll be doing: + Participate in ground breaking Processor design in deep submicron technologies. + Work as part of a global circuits team… more
- Snap Inc. (Palo Alto, CA)
- …glasses that bring augmented reality to life. We're looking for a Finite Element Analysis Engineer to join the Snap Lab team at Snap Inc! What you'll do: + Perform ... static and dynamic structural simulations using Abaqus or Ansys...hardware. + Lead and coordinate with partner teams _(Product Design , Reliability, Quality, etc.)_ to validate the predictions of… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of ... Work hard. Have Fun. Make history. At Amazon, DFT ( Design -for-Testability) is a multi-faceted job that involves architecture definition,...patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through… more
- Google (Mountain View, CA)
- …microarchitectural critical items for timing and power convergence. + Drive or develop physical design timing convergence tools and flows for advanced CPU ... Static Timing Analysis. + Experience in high speed design timing convergence and in STA tools like Primetime...that power all of Google's services. As a Hardware Engineer , you design and build the systems… more
- Microsoft Corporation (Mountain View, CA)
- …equivalence checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites within the Microsoft silicon ... team that is responsible for developing and delivering the latest Electronic Design Automation (EDA) technologies to various silicon teams within Microsoft. In this… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction. + Good understanding of Cadence ... Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should… more
- Google (Sunnyvale, CA)
- …as silicon interposer, silicon bridge, 3D die stacking. + Experience with chip top design , physical design , STA, package, system, validation teams. + ... budget methodology, including SI/PI co-analysis/ design and channel design optimization. + Understanding of Static Timing...of a larger team with Chip Architects, ASIC Engineers, Physical Design and other SI/PI Engineers. You… more
- Microsoft Corporation (Santa Clara, CA)
- …+ Review and provide feedback on verification plans and methodology. + Collaborate with Physical design teams to ensure design meets timing and area ... and partners worldwide and we are looking for passionate engineer to help achieve that mission. Are you seeking...+ Own the micro-architecture specification and RTL development of design modules for ASIC general purpose I/O block to… more
- Meta (Sunnyvale, CA)
- …for Power, Performance, and Area 17. 2. Floor Planning and Placement 18. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 ... "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/ physical synthesis using advanced… more
- Microsoft Corporation (Santa Clara, CA)
- …the Azure Hardware Systems & Infrastructure group is seeking a Principal Silicon Engineer . You will join our front-end silicon team and be responsible for delivering ... power, scalable and programmable DPU silicon. **Responsibilities** + As a Principal Silicon Engineer in the Data Processing Unit team you will be validating silicon… more
- Microsoft Corporation (Santa Clara, CA)
- …Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Silicon Engineer . You will join our front-end silicon team and be responsible for ... programmable DPU silicon. **Responsibilities** + As a Senior Silicon Engineer in the Data Processing Unit team you will...that may affect a range of feature or product design changes. Identifies possible solutions to novel and complex… more
- NVIDIA (Santa Clara, CA)
- …or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing ... technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more