- Google (Sunnyvale, CA)
- …tool workflows in semiconductor environments. + Experience developing and supporting ASIC physical design flows and methodologies in process nodes. + Experience ... and analyzing trends. + Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC integration and signoff, IP integration, chip… more
- Google (Sunnyvale, CA)
- …+ Experience leading one or more aspects of physical design or physical design flow / methodology , to successful tape-outs and shipping silicon. + ... timing ECO creation). + Experience in working across various physical design areas (ie, EDA scripting, block...+ Utilize Perl, Python, Tcl, and Bash to create flow automation scripts. + Own and maintain Primetime STA… more
- Google (Mountain View, CA)
- …(ie, Python, Bash, Tcl) for workflow automation and data visualization. + Experience with physical design flow development and design closure for ... experience. + 5 years of experience with SoC Integration focused on low power design . + Experience with new process technology based SoC integration flow … more
- NVIDIA (Santa Clara, CA)
- …our team with varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + ... and creative solutions to the state of the art physical design problems that are needed for...are needed for NVIDIA chips. + Participate in developing flow and tool methodologies for chip floorplan, power and… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the...cells/memory/IO IP modeling and its usage in the ASIC flow . Hands-on experience in advanced CMOS technologies, design… more
- NVIDIA (Santa Clara, CA)
- …EDA tools from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical synthesis, placement, routing, ... + You will be responsible for all aspects of front-end design implementation methodologies (synthesis, formal-equivalence-checking), flow automation and… more
- NVIDIA (Santa Clara, CA)
- …for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and methodology for all of NVIDIA's ... algorithms, data structures, testing + Familiarity with Verilog and ASIC and physical design along with experience in commercial EDA tools + Strong proficiency… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design ... of Python, Perl , Tcl, C/C++ + Knowledge or experience with logic synthesis, physical design , formal equivalence checking. + Proven track record developing flows… more
- Qualcomm (Santa Clara, CA)
- …flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows ... envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build...and release new features in our high-performance place-and-route CAD flow + Architect and recommend methodology improvements… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and...and/or transistor level STA as well as Experience in methodology and/or flow development/automation. The base salary… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We ... & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow ...- Should be able to work closely with IP Design teams and Backend Physical Design… more
- NVIDIA (Santa Clara, CA)
- …to build complex GPU and Tegra chips and interface, directly with unit-level ASIC, Physical Design , CAD, Package Design , Software, DFT and other teams. ... design quality checks and reviews to present the physical design team with high-quality RTL. What...are creative, collaborative, and have a real passion for design methodology and automation, we want to… more
- Qualcomm (Santa Clara, CA)
- …and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology . Involve in developing automation to improve ... Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from… more
- Qualcomm (Santa Clara, CA)
- …Python scripting skills + Strong Unix, Shell, Make skills + Knowledge of ASIC design flow & automation, testbench integration + Knowledge of low level HW/SW ... As a CAD Engineer focusing on the post silicon methodology and support, you will work with RTL, architecture,...* Leverages advanced knowledge of computer architecture, micro-architecture, logic design , circuits, and/or physical design … more
- Google (Mountain View, CA)
- …understanding of clock, reset, and power sequencing interactions. + Understanding of ASIC design flows and methodology . Our computational challenges are so big, ... more about benefits at Google (https://careers.google.com/benefits/) . + Drive power methodology for design , verification, and implementation of deep sub-micron… more
- NVIDIA (Santa Clara, CA)
- …or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis ... of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg...and clock controls in DFT modes. + Experience in methodology or flow development. NVIDIA is widely… more
- SpaceX (Sunnyvale, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +... and timing closure + Deep understanding of ASIC design flow , top-down and bottom-up design… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Amazon (Sunnyvale, CA)
- …related to DFT logic design . - Experience in Chip level DFT verification methodology and flow . - Perform SOC/IP DFT Gate-level simulations. - Static timing ... at edge. Work hard. Have Fun. Make history. At Amazon, DFT ( Design -for-Testability) is a multi-faceted job that involves architecture definition, logic design… more