- Capgemini (Santa Clara, CA)
- **Job Title: ASIC Synthesis and STA Engineer ** **Location: Santa Clara CA - Onsite role** **Job description:** We are looking for senior ASIC Synthesis and ... STA Engineer who will be responsible to...STA Engineer who will be responsible to prepare SDC and...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Synthesis and STA Engineer_ **Location:**… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer - STA to continue to innovate on behalf of our customers. We are a part ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. -… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $138,600 to… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...which is the primary task. + Develop flows/recommendations on STA and PNR in deep submicron physical effects aging,… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …maintain the timing constraint, Synthesis, Place and Route, Static timing analysis ( STA ), timing closure, power optimization, and physical verification for both of ... responsible for interfacing with the Physical Design team on STA , timing closure and P&R, and participating in silicon...timing closure flow and methodology. Strong command of synthesis, STA , design for test, and design methodologies Ability to… more
- Meta (Sunnyvale, CA)
- …stack, from transistor, through architecture, to firmware, and algorithms. As a DFT Engineer at Meta Reality Labs, you will play an integral role in implementing ... products to millions of customers quickly. **Required Skills:** DFT Engineer Responsibilities: 1. Work with the Silicon teams to...on industry standard tools 4. Work with designers on STA , physical, power and logical issues related to DFT… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using advanced optimization ... reset sequence for RDC. 8. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze the inter-block… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world! We are currently looking for a SRAM Timing Engineer to join our team of dedicated engineers developing custom SRAM circuits that help ... identify improvements and solutions and deploy newer features. + Lead implementation of STA solutions for multiple circuit design and technology teams and 3rd party… more
- Google (Sunnyvale, CA)
- …+ Experience in cross-functional collaboration with chip top design, physical design, STA , package, system design, and validation teams. + Experience in programming ... Understanding of on and off chip power delivery and STA /voltage budget. + Familiarity with memory testing, next generation...integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package… more
- Amazon (Sunnyvale, CA)
- …design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC teams to make sure the top ... equivalent experience. * 7+ years of experience in ASIC implementation, ie, synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or… more
- SpaceX (Sunnyvale, CA)
- Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of ... to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …to join us today. We are now looking for a highly motivated DFT Engineer to join this dynamic and innovative hardware team at NVIDIA. Our Design-for-Test Engineering ... vendor tools + Good exposure to multiple domains including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs +… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... how to verify them at circuit level in both spice and transistor level STA . + Understanding crosstalk, noise, OCV, timing margins, Clocking specs (jitter, IR drop,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior DFT Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the ... and IOs + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + Strong… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + Strong ... our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! The base… more
- NVIDIA (Santa Clara, CA)
- …tools. + Good exposure to multi-functional areas including RTL & clocks design, STA , place-n-route and power. + Experience in Silicon debug and bring-up on the ... our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! The base… more