- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA ... impact in a technology-focused company. What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. +… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
- NVIDIA (Santa Clara, CA)
- …devices for high-speed optical interconnect and sensing applications. + Developing physical design methodologies for implementation of graphics processors and ... includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips. + Participate in developing… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind,...in EE/CS - 5+ years of experience in developing physical design methodology or CAD… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive...sophisticated strategies of signing off timing in design for world-class silicon performance. + Develop tools, and… more
- NVIDIA (Santa Clara, CA)
- …EDA tools from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical synthesis, placement, routing, ... We are looking for a Senior CPU Implementation Methodology Engineer to...out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl,… more
- NVIDIA (Santa Clara, CA)
- … Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques ... energy usage in graphics and AI workloads and make improvements in architecture, design , and power management. What you'll be doing: + Define and implement tools… more
- NVIDIA (Santa Clara, CA)
- … needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints. What you'll be doing: + Develop Clock RTL generation ... Methodology engineer with proven experience in high-speed logic design and verification. In order to support high frequency...solutions for supporting high speed Clocking. + Understand the physical aspects of the chip and develop better clock… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition ID:**… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer, the ideal candidate will be responsible for ... signal and power EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and external teams including … more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you ... intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in...of circuits and SPICE, as well as experience in methodology and/or flow development and automation. NVIDIA is widely… more
- Cisco (San Jose, CA)
- …* Develop and analyze functional coverage. * Help define, evolve, and support our design methodology . * Collaborate with the verification team to address ... design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, debug, and… more
- Google (Mountain View, CA)
- …dependencies and deliverables. + Work closely with system, software, design , Design for testing (DFT) and physical implementation stakeholders to make ... using SystemVerilog for ASIC designs. + Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments. Preferred… more
- Cisco (San Jose, CA)
- …to meet timing and performance requirements. * Help define, evolve, and support our design methodology . * Mentor junior engineers on performing project tasks and ... address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * Perform… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer, you will ... contribute to all design phases of physical design of high performance SoC ...and isolation. + Define EM-IR signoff requirements and sign-off methodology . + Define and support Static and Dynamic, thermal,… more
- Microsoft Corporation (Santa Clara, CA)
- …(DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a ** Senior Silicon Engineer** . You will join our front-end silicon team and be ... Integrated Circuit (ASIC) System on Chip (SOC) using Universal Verification Methodology (UVM)/C test bench + Perform Pre-Silicon SoC verification, Post-Silicon/… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design ... of Python, Perl , Tcl, C/C++ + Knowledge or experience with logic synthesis, physical design , formal equivalence checking. + Proven track record developing flows… more
- Celestica (San Jose, CA)
- …& Lean; Working Effectively with Others; D/PFMEA; 8D/Corrective Action; Equipment Safety; Design of Experiments (DOE). ** Physical Demands** + Duties of this ... City: San Jose **General Overview** **Functional Area:** Engineering **Career Stream:** Design - Software Engineering **SAP Short Name:** SLE-ENG-DSE **Job Level:**… more
- Downtown Streets Team (Santa Clara County, CA)
- …not limited to; BCOE Back2Work and START Santa Clara. Partner with fellow senior directors to design and implement results-oriented program strategies that ... in Northern and Central California, serving over 1,500 people annually. SUMMARY: The Senior Director of Employment Social Enterprise (ESE) is a key leadership role,… more