• Senior RTL Analysis

    NVIDIA (Santa Clara, CA)
    …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
    NVIDIA (11/16/24)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
    NVIDIA (12/12/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis more
    NVIDIA (12/11/24)
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  • Senior Hardware Engineer

    Motion Recruitment Partners (Palo Alto, CA)
    Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer, you will contribute to all design ... subchip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry...and final physical verification. + Good knowledge of timing analysis , power analysis , physical verification (DRC/LVS), and… more
    Motion Recruitment Partners (01/17/25)
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  • Senior Power & Performance Engineer

    Microsoft Corporation (Sunnyvale, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Power and Performance Engineer** to join the team. **Responsibilities** + Work with ... power efficiency across the stack. + Develop power and performance modeling methodology by creating and owning System on Chip (SOC) architectural power models.… more
    Microsoft Corporation (01/16/25)
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  • Senior Asic Design Engineer

    Cisco (San Jose, CA)
    …and power requirements. * Contribute to full chip integration and timing methodology / analysis . * Develop and analyze functional coverage. * Help define, ... evolve, and support our design methodology . * Collaborate with the verification team to address design bugs and close code coverage. * Work closely with the physical… more
    Cisco (01/11/25)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
    NVIDIA (11/02/24)
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  • Senior E/E & Semiconductor Engineer - ASIC…

    Capgemini (San Francisco, CA)
    …of the physical chip development, executing from the inception of the design ( RTL or gate netlist) through the tape-out release to wafer fabrication using the ... complete ASIC/SOC design flow including routing, static timing closure, EM/IR analysis and chip finishing.** **Job Responsibility:** *Chip level floor planning,… more
    Capgemini (01/15/25)
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  • Sr. Staff Design Engineer (Low Power)

    Qualcomm (Santa Clara, CA)
    …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and ... their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon… more
    Qualcomm (01/09/25)
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  • Hardware Engineer 2

    Microsoft Corporation (Mountain View, CA)
    …power efficiency across the stack. + Develop in-house power and performance modelling methodology and tools for Machine Learning systems. + Project and report power ... constrained SOC performance results to senior management. + Maintain the power modeling infrastructure, used...constrained performance projections. + Work with IP Micro-architects and RTL team to incorporate low power design methodologies and… more
    Microsoft Corporation (01/10/25)
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