- Capgemini (San Francisco, CA)
- … Engineer ** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design / RTL Design engineer for our Full Time Employment ... 5 to 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 ... Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all...address timing, congestion and power issues. In-Depth Knowledge of design flow from RTL to GDSII. Good… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development. 3. RTL development using Verilog, System Verilog and HLS. 4.… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design ... process nodes. Responsibilities + Develop Quadric processor IP implementation scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer , you will ... to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power...timing, congestion and power issues. + In-Depth Knowledge of design flow from RTL to GDSII. +… more
- Siemens (San Francisco, CA)
- …or HLS using C++/systemC + 5+ years of proven hands-on experience in ASIC/FPGA design using RTL or HLS + Good understand of power, performance, area ... Req ID: 454002 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop… more
- quadric.io, Inc (Burlingame, CA)
- …floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle. ... processor architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own… more
- quadric.io, Inc (Burlingame, CA)
- …Electrical Engineering or Computer Science + 7+ years of experience in FPGA design and implementation + Experience with FPGA and/or HAPS top-level systems Vivado or ... equivalent toolchain + Experience with implementing flows to map CPU/GPU RTL on FPGA based platforms for emulation purposes Responsibilities + Develop flows to run… more
- Siemens (San Francisco, CA)
- …Req ID: 415733 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop ... the increasingly complex world of chip, board, and system design . The Story This is a unique opportunity to...criteria, committed usage upon success, run rate impact, applications engineer resources needed - all towards solving customers problem… more