- US Tech Solutions (San Francisco, CA)
- …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... **Job Description:** + The project relates to the design and verification of a custom...in analog and real number modeling preferred **Skills:** + UVM (Universal Verification Methodology) + FPGA tools… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... Description:** **Key Responsibilities:** + .Assist the design verification leads to develop software for...basic data structures and algorithms + .Hands-on experience in SystemVerilog / UVM + .Knowledge of UVM … more